OXYGENHUB
# 8799a5e4565e x16-emulator / src / disasm.c
10.8 KiB · C · last changed chore(): initial commit 15 days ago source blame history raw
03a3459e Andy McCall 1 
// Commander X16 Emulator
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// Copyright (c) 2019 Michael Steil
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// All rights reserved. License: 2-clause BSD
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#include <stdlib.h>
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#include <stdio.h>
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#include <inttypes.h>
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#include <string.h>
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#include "memory.h"
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#include "glue.h"
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#include "cpu/mnemonics.h"				// Automatically generated mnemonic table.
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// *******************************************************************************************
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//
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//		Disassemble a single 65C02/65C816 instruction into buffer. Returns the length of the
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//		instruction in total in bytes.
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//
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// *******************************************************************************************
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int disasm(uint16_t pc, uint8_t bank, uint8_t *RAM, char *line, unsigned int max_line, int16_t x16Bank, uint8_t implied_status, int32_t *eff_addr) {
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	uint8_t opcode = debug_read6502(pc, bank, x16Bank);
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	const char *mnemonic = regs.is65c816 ? mnemonics_c816[opcode] : mnemonics_c02[opcode];
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	*eff_addr = -1;
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	int isZprel = 0;
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	int isRel16 = 0;
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	int isYrel = 0;
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	int isXrel = 0;
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	int isIndirect = 0;
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	int isBlockMove = 0;
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	int isImmediate = 0;
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	int isStackRel = 0;
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	if (regs.is65c816) {
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		// Immediate opcodes (65C816)
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		switch (opcode) {
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			case 0xC2: // rep #imm8
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			case 0xE2: // sep #imm8
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				isImmediate = 1;
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				;;
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			default:
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				;;
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		}
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		// X relative opcodes (65C816)
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		switch (opcode) {
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			case 0x1F: // ora long,x
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			case 0x3F: // and long,x
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			case 0x5F: // eor long,x
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			case 0x7F: // adc long,x
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			case 0x9F: // sta long,x
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			case 0xBF: // lda long,x
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			case 0xDF: // cmp long,x
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			case 0xFC: // jsr (abs,x)
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			case 0xFF: // sbc long,x
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				isXrel = 1;
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				;;
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			default:
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				;;
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		}
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		// PER and BRL
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		switch (opcode) {
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			case 0x62: // per rel16
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			case 0x82: // brl rel16
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				isRel16 = 1;
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			default:
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				;;
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		}
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		// Y relative opcodes (65C816)
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		switch (opcode) {
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			case 0x13: // ora (zp,S),Y
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			case 0x17: // ora [zp],y
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			case 0x33: // and (zp,S),Y
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			case 0x37: // and [zp],y
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			case 0x53: // eor (zp,S),Y
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			case 0x57: // eor [zp],y
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			case 0x73: // adc (zp,S),Y
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			case 0x77: // adc [zp],y
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			case 0x93: // sta (zp,S),Y
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			case 0x97: // sta [zp],y
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			case 0xB3: // lda (zp,S),Y
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			case 0xB7: // lda [zp],y
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			case 0xD3: // cmp (zp,S),Y
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			case 0xD7: // cmp [zp],y
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			case 0xF3: // sbc (zp,S),Y
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			case 0xF7: // sbc [zp],y
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				isYrel = 1;
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				;;
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			default:
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				;;
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		}
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		// indirect opcodes (65C816)
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		switch (opcode) {
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			case 0x07: // ora [zp]
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			case 0x13: // ora (zp,S),Y
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			case 0x17: // ora [zp],y
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			case 0x27: // and [zp]
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			case 0x33: // and (zp,S),Y
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			case 0x37: // and [zp],y
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			case 0x47: // eor [zp]
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			case 0x53: // eor (zp,S),Y
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			case 0x57: // eor [zp],y
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			case 0x67: // adc [zp]
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			case 0x73: // adc (zp,S),Y
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			case 0x77: // adc [zp],y
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			case 0x87: // sta [zp]
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			case 0x93: // sta (zp,S),Y
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			case 0x97: // sta [zp],y
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			case 0xA7: // lda [zp]
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			case 0xB3: // lda (zp,S),Y
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			case 0xB7: // lda [zp],y
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			case 0xC7: // cmp [zp]
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			case 0xD3: // cmp (zp,S),Y
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			case 0xD4: // pei (zp)
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			case 0xD7: // cmp [zp],y
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			case 0xDC: // jmp [abs]
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			case 0xE7: // sbc [zp]
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			case 0xF3: // sbc (zp,S),Y
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			case 0xF7: // sbc [zp],y
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			case 0xFC: // jsr (abs,x)
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				isIndirect = 1;
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				;;
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			default:
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				;;
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		}
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		// stack-relative opcodes (65C816)
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		isStackRel = (opcode & 0x0F) == 0x03;
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		// block move (MVN and MVP)
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		isBlockMove = opcode == 0x44 || opcode == 0x54;
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	} else {
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		// BBRx and BBSx
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		isZprel = (opcode & 0x0F) == 0x0F;
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	}
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	//
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	//		The following cases are common to both 65C816 and 65C02
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	//
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	//
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	//      X relative opcodes (including indirect/indexed)
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	//
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	switch (opcode) {
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		case 0x01: // ora (zp,x)
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		case 0x15: // ora zp,x
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		case 0x16: // asl zp,x
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		case 0x1D: // ora abs,x
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		case 0x1E: // asl abs,x
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		case 0x21: // and (zp,x)
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		case 0x34: // bit zp,x
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		case 0x35: // and zp,x
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		case 0x36: // rol zp,x
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		case 0x3C: // bit abs,x
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		case 0x3D: // rol abs,x
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		case 0x41: // eor (zp,x)
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		case 0x55: // eor zp,x
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		case 0x56: // lsr zp,x
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		case 0x5d: // eor abs,x
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		case 0x5e: // lsr abs,x
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		case 0x61: // adc (zp,x)
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		case 0x74: // stz zp,x
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		case 0x75: // adc zp,x
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		case 0x76: // ror zp,x
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		case 0x7C: // jmp (abs,x)
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		case 0x7D: // adc abs,x
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		case 0x7e: // ror abs,x
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		case 0x81: // sta (zp,x)
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		case 0x94: // sty zp,x
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		case 0x95: // sta zp,x
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		case 0x9D: // sta abs,x
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		case 0x9E: // stz abs,x
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		case 0xA1: // lda (zp,x)
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		case 0xB4: // ldy zp,x
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		case 0xB5: // lda zp,x
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		case 0xBC: // ldy abs,x
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		case 0xBD: // lda abs,x
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		case 0xC1: // cmp (zp,x)
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		case 0xD5: // cmp zp,x
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		case 0xD6: // dec zp,x
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		case 0xDD: // cmp abs,x
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		case 0xDE: // dec abs,x
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		case 0xD1: // sbc (zp,x)
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		case 0xF5: // sbc zp,x
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		case 0xF6: // inc zp,x
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		case 0xFC: // jsr (abs,x)
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		case 0xFD: // sbc abs,x
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		case 0xFE: // inc abs,x
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			isXrel = 1;
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			;;
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		default:
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			;;
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	}
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	//
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	//		Test for branches, relative address. These are BRA ($80) and
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	//		$10,$30,$50,$70,$90,$B0,$D0,$F0.
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	//
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	int isRel8 = (opcode == 0x80) || ((opcode & 0x1F) == 0x10);
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	// is opcode immediate?
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	switch (opcode) {
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		case 0x09: // ora #imm
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		case 0x29: // and #imm
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		case 0x49: // eor #imm
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		case 0x69: // adc #imm
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		case 0x89: // bit #imm
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		case 0xA0: // ldy #imm
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		case 0xA2: // ldx #imm
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		case 0xA9: // lda #imm
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		case 0xC0: // cpy #imm
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		case 0xC9: // cmp #imm
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		case 0xE0: // cpx #imm
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		case 0xE9: // sbc #imm
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			isImmediate = 1;
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			;;
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		default:
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			;;
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	}
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	//      Y relative opcodes (including indirect/indexed)
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	switch (opcode) {
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		case 0x11: // ora (zp),y
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		case 0x19: // ora abs,y
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		case 0x31: // and (zp),y
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		case 0x39: // and abs,y
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		case 0x51: // eor (zp),y
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		case 0x59: // eor abs,y
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		case 0x71: // adc (zp),y
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		case 0x79: // adc abs,y
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		case 0x91: // sta (zp),y
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		case 0x96: // stx zp,y
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		case 0x99: // sta abs,y
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		case 0xB1: // lda (zp),y
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		case 0xB6: // ldx zp,y
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		case 0xB9: // lda abs,y
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		case 0xBE: // ldx abs,y
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		case 0xD1: // cmp (zp),y
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		case 0xD9: // cmp abs,y
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		case 0xF1: // sbc (zp),y
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		case 0xF9: // sbc abs,y
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			isYrel = 1;
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			;;
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		default:
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			;;
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	}
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	//	All indirect opcodes
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	switch (opcode) {
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		case 0x01: // ora (zp,x)
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		case 0x11: // ora (zp),y
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		case 0x12: // ora (zp)
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		case 0x21: // and (zp,x)
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		case 0x31: // and (zp),y
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		case 0x32: // and (zp)
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		case 0x41: // eor (zp,x)
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		case 0x51: // eor (zp),y
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		case 0x52: // eor (zp)
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		case 0x61: // adc (zp,x)
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		case 0x6C: // jmp (abs)
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		case 0x71: // adc (zp),y
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		case 0x72: // adc (zp)
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		case 0x7C: // jmp (abs,x)
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		case 0x81: // sta (zp,x)
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		case 0x91: // sta (zp),y
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		case 0x92: // sta (zp)
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		case 0xA1: // lda (zp,x)
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		case 0xB1: // lda (zp),y
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		case 0xB2: // lda (zp)
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		case 0xC1: // cmp (zp,x)
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		case 0xD1: // cmp (zp),y
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		case 0xD2: // cmp (zp)
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		case 0xE1: // sbc (zp,x)
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		case 0xF1: // sbc (zp),y
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		case 0xF2: // sbc (zp)
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			isIndirect = 1;
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			;;
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		default:
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			;;
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	}
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	// BRK and COP (works with 65C02 as well since it's a nop #imm8)
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	int isBrkOrCop = opcode == 0x00 || opcode == 0x02;
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	int length = 1;
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	char *where = strstr(mnemonic, "%%0%hhux");
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	if (where) {
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		int isImmediateIndex = (opcode == 0xa0) || (opcode == 0xa2) || (opcode == 0xc0) || (opcode == 0xe0);
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		int len = snprintf(line, max_line, mnemonic, (implied_status & (isImmediateIndex ? FLAG_INDEX_WIDTH : FLAG_MEMORY_WIDTH)) ? 2 : 4);
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		if (len == -1) {
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			return 0;
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		}
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		mnemonic = malloc(len + 1);
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		memcpy((char *) mnemonic, line, len + 1);
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	}
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	else {
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		strncpy(line,mnemonic,max_line);
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	}
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	if (isBlockMove) {
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		snprintf(line, max_line, mnemonic, debug_read6502(pc + 2, bank, x16Bank), debug_read6502(pc + 1, bank, x16Bank));
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		length = 3;
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		if (regs.c != 0xFFFF) *eff_addr = regs.y; // We can have only one effective address, so we're choosing the destination
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	}
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	else if (isZprel) {
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		snprintf(line, max_line, mnemonic, debug_read6502(pc + 1, bank, x16Bank), pc + 3 + (int8_t)debug_read6502(pc + 2, bank, x16Bank));
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		length = 3;
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	}
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	else if (isRel16) {
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		snprintf(line, max_line, mnemonic, (pc + 3 + (int16_t)(debug_read6502(pc + 1, bank, x16Bank) | (debug_read6502(pc + 2, bank, x16Bank) << 8))) & 0xffff);
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		length = 3;
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	}
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	else if (isBrkOrCop) {
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		snprintf(line, max_line, mnemonic, debug_read6502(pc + 1, bank, x16Bank));
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		length = 2;
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	} else {
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		if (strstr(line, "%02x")) {
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			length = 2;
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			if (isRel8) {
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				snprintf(line, max_line, mnemonic, pc + 2 + (int8_t)debug_read6502(pc + 1, bank, x16Bank));
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			} else {
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				snprintf(line, max_line, mnemonic, debug_read6502(pc + 1, bank, x16Bank));
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				if (isStackRel) {
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					uint16_t ptr = regs.sp + debug_read6502(pc + 1, bank, x16Bank);
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					uint8_t ind_bank = ptr < 0xc000 ? memory_get_ram_bank() : memory_get_rom_bank();
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					if (isIndirect && isYrel) {
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						*eff_addr = (debug_read6502(ptr, bank, ind_bank) | (debug_read6502(ptr + 1, bank, ind_bank) << 8)) + regs.y;
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					} else {
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						*eff_addr = ptr;
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					}
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				} else if (isIndirect) {
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					uint16_t ptr = debug_read6502(pc + 1, bank, x16Bank);
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					if (isXrel)
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						ptr += regs.x;
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					*eff_addr = debug_read6502(ptr, bank, x16Bank) | (debug_read6502(ptr + 1, bank, x16Bank) << 8);
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					if (isYrel)
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						*eff_addr += regs.y;
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				} else if (!isImmediate) {
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					*eff_addr = debug_read6502(pc + 1, bank, x16Bank);
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					if (isXrel)
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						*eff_addr += regs.x;
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					if (isYrel)
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						*eff_addr += regs.y;
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				}
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			}
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		}
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		if (strstr(line, "%04x")) {
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			length = 3;
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			snprintf(line, max_line, mnemonic, debug_read6502(pc + 1, bank, x16Bank) | debug_read6502(pc + 2, bank, x16Bank) << 8);
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			if (isIndirect) {
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				uint16_t ptr = debug_read6502(pc + 1, bank, x16Bank) | (debug_read6502(pc + 2, bank, x16Bank) << 8);
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				if (isXrel)
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					ptr += regs.x;
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				uint8_t ind_bank = ptr < 0xc000 ? memory_get_ram_bank() : memory_get_rom_bank();
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				*eff_addr = debug_read6502(ptr, bank, ind_bank) | (debug_read6502(ptr + 1, bank, ind_bank) << 8);
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				if (isYrel)
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					*eff_addr += regs.y;
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			} else if (!isImmediate) {
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				*eff_addr = debug_read6502(pc + 1, bank, x16Bank) | (debug_read6502(pc + 2, bank, x16Bank) << 8);
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				if (isXrel)
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					*eff_addr += regs.x;
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				if (isYrel)
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					*eff_addr += regs.y;
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			}
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		}
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		if (strstr(line, "%06x")) {
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			length = 4;
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			snprintf(line, max_line, mnemonic, debug_read6502(pc + 1, bank, x16Bank) | debug_read6502(pc + 2, bank, x16Bank) << 8 | debug_read6502(pc + 3, bank, x16Bank) << 16);
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			if (isIndirect) {
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				uint16_t ptr = debug_read6502(pc + 1, bank, x16Bank) | (debug_read6502(pc + 2, bank, x16Bank) << 8);
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				if (isXrel)
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					ptr += regs.x;
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				uint8_t ind_bank = ptr < 0xc000 ? memory_get_ram_bank() : memory_get_rom_bank();
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				*eff_addr = debug_read6502(ptr, bank, ind_bank) | (debug_read6502(ptr + 1, bank, ind_bank) << 8);
385 
				if (isYrel)
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					*eff_addr += regs.y;
387 
			} else {
388 
				*eff_addr = debug_read6502(pc + 1, bank, x16Bank) | (debug_read6502(pc + 2, bank, x16Bank) << 8);
389 
				if (isXrel)
390 
					*eff_addr += regs.x;
391 
				if (isYrel)
392 
					*eff_addr += regs.y;
393 
			}
394 
		}
395 
		if (opcode == 0x00 || opcode == 0x02) {
396 
			// BRK and COP instructions are 2 bytes long according to WDC datasheet.
397 
			// CPU skips the second byte when it executes a BRK / COP.
398 
			length = 2;
399 
		}
400 
	}
401
402 
	if (where) {
403 
		free((char *) mnemonic);
404 
	}
405
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	if (*eff_addr >= 0x10000) {
407 
		*eff_addr &= 0xffff;
408 
	}
409
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	return length;
411 
}