OXYGENHUB
◆ rrdc-perf enhanced-x16-emulator / src / memory.c
20.9 KiB · C · last changed chore(): initial commit 25 days ago source blame history raw
9120e874 Andy McCall 1 
// Commander X16 Emulator
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// Copyright (c) 2019 Michael Steil
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// All rights reserved. License: 2-clause BSD
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#include <sys/types.h>
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#include <string.h>
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#include <stdlib.h>
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#include "compat.h"
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#include <time.h>
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#include <inttypes.h>
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#include "glue.h"
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#include "dbg_load.h"
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#include "via.h"
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#include "memory.h"
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#include "video.h"
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#include "ymglue.h"
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#include "cpu/fake6502.h"
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#include "wav_recorder.h"
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#include "audio.h"
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#include "cartridge.h"
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#include "iso_8859_15.h"
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#include "midi.h"
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#include "debug_core.h"
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#include "debugger.h"
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#include "io_trace.h"
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#include "perf_budget.h"
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uint8_t ram_bank;
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uint8_t rom_bank;
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uint8_t *RAM, *BRAM;
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uint8_t ROM[ROM_SIZE];
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extern uint8_t *CART;
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static uint8_t addr_ym = 0;
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// Defined below, next to the I/O dispatch it belongs to; declared here because
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// memory_init() installs it.
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static void io_trace_cpu_context(uint16_t *pc, uint8_t *pc_bank, uint32_t *cycles);
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bool randomizeRAM = false;
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bool reportUninitializedAccess = false;
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const char *reportUsageStatisticsFilename = NULL;
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bool *RAM_access_flags, *BRAM_access_flags;
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uint64_t *RAM_system_reads;
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uint64_t *RAM_system_writes;
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uint64_t *RAM_banked_reads[256];
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uint64_t *RAM_banked_writes[256];
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uint64_t *ROM_banked_reads[256];
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uint64_t *ROM_banked_writes[256];	// shouldn't occur for obvious reasons unless Bonk RAM is installed in a cart
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static uint32_t clock_snap = 0UL;
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static uint32_t clock_base = 0UL;
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#define DEVICE_EMULATOR (0x9fb0)
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void cpuio_write(uint8_t reg, uint8_t value);
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void
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memory_init()
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{
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	// The trace stamps each event with the PC and cycle count, which io_trace.c
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	// cannot reach for itself without pulling the CPU into every target that
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	// links memory.c -- including the two unit tests that pair it with fake
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	// devices. Handing it a provider keeps that module dependency-free.
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	io_trace_set_context_provider(io_trace_cpu_context);
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	// Initialize RAM array
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	RAM = calloc(RAM_SIZE, sizeof(uint8_t));
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	BRAM = calloc(BRAM_SIZE, sizeof(uint8_t));
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	if(reportUsageStatisticsFilename!=NULL) {
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		RAM_system_reads = calloc(num_banks * BANK_SIZE, sizeof(uint64_t));
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		RAM_system_writes = calloc(num_banks * BANK_SIZE, sizeof(uint64_t));
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		for(int bank=0; bank<256; ++bank) {
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			RAM_banked_reads[bank] = calloc(8192, sizeof(uint64_t));
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			RAM_banked_writes[bank] = calloc(8192, sizeof(uint64_t));
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			ROM_banked_reads[bank] = calloc(16384, sizeof(uint64_t));
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			ROM_banked_writes[bank] = calloc(16384, sizeof(uint64_t));
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		}
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	}
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	// Randomize all RAM (if option selected)
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	if (randomizeRAM) {
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		time_t t;
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		srand((unsigned)time(&t));
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		for (int i = 0; i < RAM_SIZE; i++) {
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			if (i >= 0x9f00 && i < 0x10000) {
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				// Leave the unused hole in the address space at 0
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				// Memory dumps will likely confuse people less often
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				RAM[i] = 0;
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			} else {
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				RAM[i] = rand();
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			}
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		}
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		for (int i = 0; i < BRAM_SIZE; i++) {
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			BRAM[i] = rand();
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		}
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	}
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	// Initialize RAM access flag array (if option selected)
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	if (reportUninitializedAccess) {
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		RAM_access_flags = (bool*) malloc(RAM_SIZE * sizeof(bool));
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		for (int i = 0; i < RAM_SIZE; i++) {
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			RAM_access_flags[i] = false;
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		}
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		BRAM_access_flags = (bool*) malloc(BRAM_SIZE * sizeof(bool));
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		for (int i = 0; i < BRAM_SIZE; i++) {
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			BRAM_access_flags[i] = false;
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		}
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	}
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	memory_reset();
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}
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void
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memory_reset()
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{
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	// default banks are 0
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	memory_set_ram_bank(0);
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	memory_set_rom_bank(0);
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}
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void
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memory_report_uninitialized_access(bool value)
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{
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	reportUninitializedAccess = value;
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}
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void
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memory_report_usage_statistics(const char *filename) {
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	reportUsageStatisticsFilename = filename;
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}
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void
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memory_randomize_ram(bool value)
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{
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	randomizeRAM = value;
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}
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void
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memory_initialize_cart(uint8_t *mem)
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{
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	if(randomizeRAM) {
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		for(int i=0; i<0x4000; ++i) {
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			mem[i] = rand();
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		}
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	} else {
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		memset(mem, 0, 0x4000);
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	}
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}
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//
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// interface for fake6502
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//
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// if debugOn then reads memory only for debugger; no I/O, no side effects whatsoever
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static const char *format_addr(uint16_t address, uint8_t bank, uint8_t x16Bank) {
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	static char buffer[2 + 1 + 4 + 1];
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	if (bank == 0 && address >= 0xA000) {
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		if (address >= 0xA000) {
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			snprintf(buffer, sizeof(buffer), "%02X:%04X", x16Bank, address);
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		}
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	}
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	else if (is_gen2) {
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		snprintf(buffer, sizeof(buffer), "%02X %04X", bank, address);
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	} else {
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		snprintf(buffer, sizeof(buffer), "%04X", address);
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	}
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	return buffer;
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}
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uint8_t
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read6502(uint16_t address, uint8_t bank) {
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	if (!is_gen2) bank = 0;
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	// Report access to uninitialized RAM (if option selected)
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	if (reportUninitializedAccess) {
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		if (bank == 0) {
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			uint8_t pc_x16_bank;
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			if (opcode_addr < 0xa000) {
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				pc_x16_bank = 0;
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			} else if (opcode_addr < 0xc000) {
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				pc_x16_bank = memory_get_ram_bank();
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			} else {
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				pc_x16_bank = memory_get_rom_bank();
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			}
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			if (address >= 0xa000 && address < 0xc000) {
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				if (memory_get_ram_bank() < num_ram_banks && BRAM_access_flags[(memory_get_ram_bank() << 13) + address - 0xa000] == false){
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					printf("Warning: %02X:%04X accessed uninitialized RAM address %02X:%04X\n", pc_x16_bank, opcode_addr, memory_get_ram_bank(), address);
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				}
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			}
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		}
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		if (bank != 0 || address < 0x9f00) {
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			if (RAM_access_flags[bank * BANK_SIZE + address] == false) {
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				printf("Warning: %s accessed uninitialized RAM address %02X %04X\n", format_addr(opcode_addr, regs.k, 0), bank, address);
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			}
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		}
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	}
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    if (reportUsageStatisticsFilename!=NULL) {
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      if (bank != 0 || address < 0xa000) {
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        RAM_system_reads[bank * BANK_SIZE + address]++;
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      } else if (address < 0xc000) {
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        RAM_banked_reads[memory_get_ram_bank()][address-0xa000]++;
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      } else {
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		ROM_banked_reads[rom_bank][address-0xc000]++;
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      }
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    }
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	return real_read6502(address, bank, false, USE_CURRENT_X16_BANK);
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}
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// Which device an I/O-page address belongs to, for the trace. Kept here rather
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// than in io_trace.c because the MIDI card's base address is configurable, so
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// only the dispatch below actually knows the map.
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//
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// $9F3E/$9F3F are reported as IO_DEV_SPI, not IO_DEV_VERA: they are VERA
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// registers, but they are also the sole path to the SD card, and VERA capture
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// is off by default because its data ports would swamp the ring.
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static io_device_t
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io_trace_device_for(uint16_t address)
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{
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	if (address >= 0x9f00 && address < 0x9f10) {
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		return IO_DEV_VIA1;
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	} else if (has_via2 && address >= 0x9f10 && address < 0x9f20) {
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		return IO_DEV_VIA2;
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	} else if (address >= 0x9f3e && address < 0x9f40) {
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		return IO_DEV_SPI;
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	} else if (address >= 0x9f20 && address < 0x9f40) {
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		return IO_DEV_VERA;
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	} else if (address >= 0x9f40 && address < 0x9f60) {
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		return (address & 0x01) != 0 ? IO_DEV_YM : IO_DEV_OPENBUS;
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	} else if (address >= 0x9fb0 && address < 0x9fc0) {
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		return IO_DEV_EMU;
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	} else if (has_midi_card && (address & 0xfff0) == midi_card_addr) {
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		return IO_DEV_MIDI;
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	}
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	return IO_DEV_OPENBUS;
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}
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// Stamps trace events with where the machine was when they happened. Installed
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// from memory_init() so io_trace.c itself need not know about the CPU.
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static void
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io_trace_cpu_context(uint16_t *pc, uint8_t *pc_bank, uint32_t *cycles)
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{
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	*pc      = regs.pc;
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	*pc_bank = regs.k;
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	*cycles  = clockticks6502;
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}
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// The I/O page dispatch, lifted out of real_read6502() so the value it produces
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// can be traced. Reads here have side effects -- VERA's data ports
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// auto-increment, the SPI port consumes a byte -- so the caller records what
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// this returned and never re-reads to find out.
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static uint8_t
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io_read(uint16_t address, bool debugOn)
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{
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	if (!debugOn && address >= 0x9fa0) {
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		// slow IO5-7 range
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		clockticks6502 += 3;
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	}
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	if (address >= 0x9f00 && address < 0x9f10) {
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		return via1_read(address & 0xf, debugOn);
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	} else if (has_via2 && (address >= 0x9f10 && address < 0x9f20)) {
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		return via2_read(address & 0xf, debugOn);
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	} else if (address >= 0x9f20 && address < 0x9f40) {
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		return video_read(address & 0x1f, debugOn);
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	} else if (address >= 0x9f40 && address < 0x9f60) {
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		// slow IO2 range
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		if (!debugOn) {
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			clockticks6502 += 3;
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		}
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		if ((address & 0x01) != 0) { // partial decoding in this range
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			// A debug read must not flush audio: audio_render() advances
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			// the render write position, and the "no side effects"
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			// guarantee is what lets the debugger sweep the I/O page.
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			if (!debugOn) {
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				audio_render();
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			}
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			return YM_read_status();
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		}
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		return 0x9f; // open bus read
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	} else if (address >= 0x9fb0 && address < 0x9fc0) {
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		// emulator state
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		return emu_read(address & 0xf, debugOn);
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	} else if (has_midi_card && (address & 0xfff0) == midi_card_addr) {
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		// midi card
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		return midi_serial_read(address & 0xf, debugOn);
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	} else {
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		// future expansion
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		return 0x9f; // open bus read
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	}
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}
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uint8_t
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real_read6502(uint16_t address, uint8_t bank, bool debugOn, int16_t x16Bank)
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{
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	if (is_gen2 && bank != 0) { // RAM
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		if (bank < num_banks) {
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			return RAM[bank * BANK_SIZE + address];
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		} else {
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			return (address >> 8) & 0xff; // open bus read
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		}
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	}
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	if (address < 0x9f00) { // RAM
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		return RAM[address];
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	} else if (address < 0xa000) { // I/O
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		const uint8_t value = io_read(address, debugOn);
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		// A debug read stays out of the trace entirely. The trace records what
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		// the machine did; the debugger sweeping the I/O page to draw itself is
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		// not the machine, and letting it in would mean the act of watching
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		// filled the ring with its own observations.
321 
		if (!debugOn) {
322 
			const io_device_t dev = io_trace_device_for(address);
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			if (io_trace_wants(dev)) {
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				io_trace_access(dev, address, value, false);
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			}
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		}
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		return value;
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	} else if (address < 0xc000) { // banked RAM
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		int ramBank = x16Bank >= 0 ? (uint8_t)x16Bank : memory_get_ram_bank();
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		if (ramBank < num_ram_banks) {
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			return BRAM[(ramBank << 13) + address - 0xa000];
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		} else {
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			return (address >> 8) & 0xff; // open bus read
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		}
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	} else { // banked ROM
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		int romBank = x16Bank >= 0 ? (uint8_t)x16Bank : rom_bank;
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		if (romBank < 32) {
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			return ROM[(romBank << 14) + address - 0xc000];
339 
		} else {
340 
			if (!CART) {
341 
				return (address >> 8) & 0xff; // open bus read
342 
			}
343 
			return cartridge_read(address, romBank);
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		}
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	}
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}
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void
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write6502(uint16_t address, uint8_t bank, uint8_t value)
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{
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	real_write6502(address, bank, value, false);
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}
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void
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real_write6502(uint16_t address, uint8_t bank, uint8_t value, bool debugOn)
356 
{
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	if (!is_gen2) bank = 0;
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	if(reportUsageStatisticsFilename!=NULL) {
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		if (bank != 0 || address < 0xa000) {
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			RAM_system_writes[bank * BANK_SIZE + address]++;
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		} else if (address < 0xc000) {
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			RAM_banked_writes[memory_get_ram_bank()][address-0xa000]++;
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		} else {
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			// this is weird, but it does occur. And cartridges can install "Bonk RAM" in place of ROM.
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			ROM_banked_writes[rom_bank][address-0xc000]++;
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		}
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	}
369
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	// Update RAM access flag
371 
	if (reportUninitializedAccess) {
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		if (bank != 0 || address < 0xa000) {
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			RAM_access_flags[bank * BANK_SIZE + address] = true;
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		} else if (address < 0xc000) {
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			if (memory_get_ram_bank() < num_ram_banks)
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				BRAM_access_flags[(memory_get_ram_bank() << 13) + address - 0xa000] = true;
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		}
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	}
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	// Memory write watchpoints. The scan is skipped entirely while none are
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	// set, so this costs one comparison per store outside a debugging session.
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	// Only bank 0 is watched: a non-zero program bank on Gen2 is flat RAM in a
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	// separate address space, which a 16-bit watch address cannot name.
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	//
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	// A debug write is not a store the program made, so it reports nothing: a
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	// watchpoint answers "when does the program touch this?", and breaking on
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	// the debugger's own edit answers a question nobody asked.
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	if (!debugOn && debug_wp_count() > 0 && bank == 0 && debug_wp_check_write(address, value)) {
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		DEBUGBreakOnWatchpoint();
390 
	}
391
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	// A store is the signal the budget's spin detector runs on: a loop that
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	// writes nothing is waiting, and a loop that writes is computing. A debug
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	// write is excluded for the same reason it is excluded from watchpoints and
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	// the I/O trace -- the debugger poking memory is not the program running.
396 
	if (!debugOn) {
397 
		perf_budget_note_store();
398 
	}
399
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	// Write to memory
401 
	if (is_gen2 && bank != 0) {
402 
		if (bank < num_banks) {
403 
			RAM[bank * BANK_SIZE + address] = value;
404 
		}
405 
		return;
406 
	}
407
408 
	// Write to CPU I/O ports
409 
	if (address < 2) {
410 
		cpuio_write(address, value);
411 
	}
412 
	// Write to memory
413 
	if (address < 0x9f00) { // RAM
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		RAM[address] = value;
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	} else if (address < 0xa000) { // I/O
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		// Traced before dispatch, so that a decoded event the device emits in
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		// response -- an SD command completing, a file being opened -- is
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		// ordered after the write that caused it.
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		//
420 
		// A debug write stays out of the trace for the same reason a debug read
421 
		// does: the trace records what the machine did, and the debugger poking
422 
		// a register on the user's behalf is not the machine.
423 
		if (!debugOn) {
424 
			const io_device_t dev = io_trace_device_for(address);
425 
			if (io_trace_wants(dev)) {
426 
				io_trace_access(dev, address, value, true);
427 
			}
428 
		}
429 
		if (!debugOn && address >= 0x9fa0) {
430 
			// slow IO5-7 range
431 
			clockticks6502 += 3;
432 
		}
433 
		if (address >= 0x9f00 && address < 0x9f10) {
434 
			via1_write(address & 0xf, value);
435 
		} else if (has_via2 && (address >= 0x9f10 && address < 0x9f20)) {
436 
			via2_write(address & 0xf, value);
437 
		} else if (address >= 0x9f20 && address < 0x9f40) {
438 
			// video_write() has no debugOn parameter -- eighty-odd call sites
439 
			// would have to change to give it one -- so the debugger announces
440 
			// itself instead. VERA's bandwidth accounting must not charge the
441 
			// guest for a poke the developer made from a memory view.
442 
			video_set_debug_write(debugOn);
443 
			video_write(address & 0x1f, value);
444 
			video_set_debug_write(false);
445 
		} else if (address >= 0x9f40 && address < 0x9f60) {
446 
			// slow IO2 range
447 
			if (!debugOn) {
448 
				clockticks6502 += 3;
449 
			}
450 
			if ((address & 0x01) == 0) {   // YM reg (partially decoded)
451 
				addr_ym = value;
452 
			} else {                       // YM data (partially decoded)
453 
				audio_render();
454 
				YM_write_reg(addr_ym, value);
455 
			}
456 
		} else if (address >= 0x9fb0 && address < 0x9fc0) {
457 
			// emulator state
458 
			emu_write(address & 0xf, value);
459 
		} else if (has_midi_card && (address & 0xfff0) == midi_card_addr) {
460 
			midi_serial_write(address & 0xf, value);
461 
		} else {
462 
			// future expansion
463 
		}
464 
	} else if (address < 0xc000) { // banked RAM
465 
		if (memory_get_ram_bank() < num_ram_banks) {
466 
			BRAM[(memory_get_ram_bank() << 13) + address - 0xa000] = value;
467 
		}
468 
	} else { // ROM
469 
		if (rom_bank >= 32) { // Cartridge ROM/RAM
470 
			cartridge_write(address, rom_bank, value);
471 
		}
472 
		// ignore if base ROM (banks 0-31)
473 
	}
474 
}
475
476 
void
477 
vp6502()
478 
{
479 
	memory_set_rom_bank(0);
480 
}
481
482 
//
483 
// saves the memory content into a file
484 
//
485
486 
void
487 
memory_save(SDL_RWops *f, bool dump_ram, bool dump_bank)
488 
{
489 
	if (dump_ram) {
490 
		SDL_RWwrite(f, &RAM[0], sizeof(uint8_t), is_gen2 ? num_banks * BANK_SIZE : 0xa000);
491 
	}
492 
	if (dump_bank) {
493 
		SDL_RWwrite(f, &BRAM[0], sizeof(uint8_t), (num_ram_banks * 8192));
494 
	}
495 
}
496
497
498 
void writestring(SDL_RWops *f, const char *string) {
499 
	SDL_RWwrite(f, string, strlen(string), 1);
500 
}
501
502 
void memory_dump_usage_counts() {
503 
	if(reportUsageStatisticsFilename==NULL)
504 
		return;
505
506 
	SDL_RWops *f = SDL_RWFromFile(reportUsageStatisticsFilename, "w");
507 
	if (!f) {
508 
		printf("Cannot write to %s!\n", reportUsageStatisticsFilename);
509 
		return;
510 
	}
511
512 
	writestring(f, "Usage counts of all memory locations. Locations not printed have count zero.\n");
513 
	writestring(f, "Tip: use 'sort -r -n -k 3' to sort it so it shows the most used at the top.\n");
514 
	writestring(f, "\nsystem RAM reads:\n");
515 
	int addr;
516 
	char buf[100];
517 
	for(addr=0; addr<num_banks * BANK_SIZE; ++addr) {
518 
		if(RAM_system_reads[addr]>0) {
519 
			SDL_RWwrite(f, buf, snprintf(buf, sizeof(buf), "r %04x %" PRIu64 "\n", addr, RAM_system_reads[addr]), 1);
520 
		}
521 
	}
522 
	writestring(f, "\nsystem RAM writes:\n");
523 
	for(addr=0; addr<65536; ++addr) {
524 
		if(RAM_system_writes[addr]>0) {
525 
			SDL_RWwrite(f, buf, snprintf(buf, sizeof(buf), "w %04x %" PRIu64 "\n", addr, RAM_system_writes[addr]), 1);
526 
		}
527 
	}
528 
	writestring(f, "\nbanked RAM reads:\n");
529 
	int bank;
530 
	for(bank=0; bank<256; ++bank) {
531 
		for(addr=0; addr<8192; ++addr) {
532 
			if(RAM_banked_reads[bank][addr]>0) {
533 
				SDL_RWwrite(f, buf, snprintf(buf, sizeof(buf), "r %02x:%04x %" PRIu64 "\n", bank, addr+0xa000, RAM_banked_reads[bank][addr]), 1);
534 
			}
535 
		}
536 
	}
537 
	writestring(f, "\nbanked RAM writes:\n");
538 
	for(bank=0; bank<256; ++bank) {
539 
		for(addr=0; addr<8192; ++addr) {
540 
			if(RAM_banked_writes[bank][addr]>0) {
541 
				SDL_RWwrite(f, buf, snprintf(buf, sizeof(buf), "w %02x:%04x %" PRIu64 "\n", bank, addr+0xa000, RAM_banked_writes[bank][addr]), 1);
542 
			}
543 
		}
544 
	}
545 
	writestring(f, "\nbanked ROM reads:\n");
546 
	for(bank=0; bank<256; ++bank) {
547 
		for(addr=0; addr<16384; ++addr) {
548 
			if(ROM_banked_reads[bank][addr]>0) {
549 
				SDL_RWwrite(f, buf, snprintf(buf, sizeof(buf), "r %02x:%04x %" PRIu64 "\n", bank, addr+0xc000, ROM_banked_reads[bank][addr]), 1);
550 
			}
551 
		}
552 
	}
553 
	writestring(f, "\nbanked ROM / 'Bonk RAM' writes:\n");
554 
	for(bank=0; bank<256; ++bank) {
555 
		for(addr=0; addr<16384; ++addr) {
556 
			if(ROM_banked_writes[bank][addr]>0) {
557 
				SDL_RWwrite(f, buf, snprintf(buf, sizeof(buf), "w %02x:%04x %" PRIu64 "\n", bank, addr+0xc000, ROM_banked_writes[bank][addr]), 1);
558 
			}
559 
		}
560 
	}
561
562 
	SDL_RWclose(f);
563 
}
564
565
566 
///
567 
///
568 
///
569
570 
inline void
571 
memory_set_ram_bank(uint8_t bank)
572 
{
573 
	ram_bank = bank;
574 
}
575
576 
inline uint8_t
577 
memory_get_ram_bank()
578 
{
579 
	return ram_bank;
580 
}
581
582 
inline void
583 
memory_set_rom_bank(uint8_t bank)
584 
{
585 
	rom_bank = bank;
586 
}
587
588 
inline uint8_t
589 
memory_get_rom_bank()
590 
{
591 
	return rom_bank;
592 
}
593
594 
void
595 
cpuio_write(uint8_t reg, uint8_t value)
596 
{
597 
	switch (reg) {
598 
		case 0:
599 
			memory_set_ram_bank(value);
600 
			break;
601 
		case 1:
602 
			memory_set_rom_bank(value);
603 
			break;
604 
	}
605 
}
606
607 
// Control the GIF recorder
608 
void
609 
emu_recorder_set(gif_recorder_command_t command)
610 
{
611 
	// turning off while recording is enabled
612 
	if (command == RECORD_GIF_PAUSE && record_gif != RECORD_GIF_DISABLED) {
613 
		record_gif = RECORD_GIF_PAUSED; // need to save
614 
	}
615 
	// turning on continuous recording
616 
	if (command == RECORD_GIF_RESUME && record_gif != RECORD_GIF_DISABLED) {
617 
		record_gif = RECORD_GIF_ACTIVE;		// activate recording
618 
	}
619 
	// capture one frame
620 
	if (command == RECORD_GIF_SNAP && record_gif != RECORD_GIF_DISABLED) {
621 
		record_gif = RECORD_GIF_SINGLE;		// single-shot
622 
	}
623 
}
624
625 
//
626 
// read/write emulator state (feature flags)
627 
//
628 
// 0: debugger_enabled
629 
// 1: log_video
630 
// 2: log_keyboard
631 
// 3: echo_mode
632 
// 4: save_on_exit
633 
// 5: record_gif
634 
// 6: record_wav
635 
// 7: cmd key toggle
636 
// 8: write: reset cpu clock counter
637 
// 8: read: snapshots cpu clock counter and reads the LSB bits 0-7
638 
// 9: write: output debug byte 1
639 
// 9: read: cpu clock bits 8-15
640 
// 10: write: output debug byte 2
641 
// 10: read: cpu clock bits 16-23
642 
// 11: write: write character to STDOUT of console
643 
// 11: read: cpu clock MSB bits 24-31
644 
// 12: write: performance budget marker (see perf_budget.h for the protocol)
645 
// 12: read: marker protocol version, so guest code can feature-detect
646 
// POKE $9FB3,1:PRINT"ECHO MODE IS ON":POKE $9FB3,0
647 
void
648 
emu_write(uint8_t reg, uint8_t value)
649 
{
650 
	bool v = value != 0;
651 
	switch (reg) {
652 
		// Also told to dbg_load: it follows the debugger by default, and the
653 
		// machine can switch the debugger on here long after startup. The
654 
		// graphical debugger counts as "a debugger is on" too, so a guest
655 
		// clearing this register must not switch .dbg loading off underneath
656 
		// a running -imgui session.
657 
		case 0: debugger_enabled = v; dbg_load_note_debugger(v || imgui_debugger_enabled); break;
658 
		case 1: log_video = v; break;
659 
		case 2: log_keyboard = v; break;
660 
		case 3: echo_mode = value; break;
661 
		case 4: save_on_exit = v; break;
662 
		case 5: emu_recorder_set((gif_recorder_command_t) value); break;
663 
		case 6: wav_recorder_set((wav_recorder_command_t) value); break;
664 
		case 7: disable_emu_cmd_keys = v; break;
665 
		case 8: clock_base = clockticks6502; break;
666 
		case 9: printf("User debug 1: $%02x\n", value); fflush(stdout); break;
667 
		case 10: printf("User debug 2: $%02x\n", value); fflush(stdout); break;
668 
		case 11: {
669 
			if (value == 0x09 || value == 0x0a || value == 0x0d || (value >= 0x20 && value < 0x7f)) {
670 
				printf("%c", value);
671 
			} else if (value >= 0xa1) {
672 
				print_iso8859_15_char((char) value);
673 
			} else {
674 
				printf("\xef\xbf\xbd"); // �
675 
			}
676 
			fflush(stdout);
677 
			break;
678 
		}
679 
		case 12: perf_budget_marker_write(value); break;
680 
		default: printf("WARN: Invalid register %x\n", DEVICE_EMULATOR + reg);
681 
	}
682 
}
683
684 
uint8_t
685 
emu_read(uint8_t reg, bool debugOn)
686 
{
687 
	if (reg == 0) {
688 
		return debugger_enabled ? 1 : 0;
689 
	} else if (reg == 1) {
690 
		return log_video ? 1 : 0;
691 
	} else if (reg == 2) {
692 
		return log_keyboard ? 1 : 0;
693 
	} else if (reg == 3) {
694 
		return echo_mode;
695 
	} else if (reg == 4) {
696 
		return save_on_exit ? 1 : 0;
697 
	} else if (reg == 5) {
698 
		return record_gif;
699 
	} else if (reg == 6) {
700 
		return wav_recorder_get_state();
701 
	} else if (reg == 7) {
702 
		return disable_emu_cmd_keys ? 1 : 0;
703
704 
	} else if (reg == 8) {
705 
		if (!debugOn)
706 
			clock_snap = clockticks6502 - clock_base;
707 
		return (clock_snap >> 0) & 0xff;
708 
	} else if (reg == 9) {
709 
		return (clock_snap >> 8) & 0xff;
710 
	} else if (reg == 10) {
711 
		return (clock_snap >> 16) & 0xff;
712 
	} else if (reg == 11) {
713 
		return (clock_snap >> 24) & 0xff;
714
715 
	} else if (reg == 12) {
716 
		return perf_budget_marker_read();
717 
	} else if (reg == 13) {
718 
		return keymap;
719 
	} else if (reg == 14) {
720 
		return '1'; // emulator detection
721 
	} else if (reg == 15) {
722 
		return '6'; // emulator detection
723 
	}
724 
	if (!debugOn) printf("WARN: Invalid register %x\n", DEVICE_EMULATOR + reg);
725 
	return -1;
726 
}