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EX (SP),HL
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==========
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This instruction does 5 memory transactions
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 - 1 byte instruction fetch
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 - 2 bytes data reads
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 - 2 bytes data writes
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The goal of this test is to find out the order of these 5 transactions.
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Obviously the instruction fetch (F) is the first transaction.
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There is one read from location SP+0, I'll call this R0. One read from
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location SP+1 (R0). A write to SP+0 (W0) and a write to SP+1 (W1).
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R0 must come before WO and R1 must come before W1. This leaves the
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following possible orders (please check that I didn't miss some):
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  a) F R0 W0 R1 W1
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  b) F R0 R1 W0 W1
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  c) F R0 R1 W1 W0
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  d) F R1 W1 R0 W0
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  e) F R1 R0 W1 W0
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  f) F R1 R0 W0 W1
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* Z80
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In the document z80cpu_um.pdf you can find the number of cycles per M-cycle.
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For the EX (SP),HL instruction it lists:
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  5 M-cycles, 19 T-states, 4+3+4+3+5
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  note: this doesn't include the extra wait-state introduced on MSX.
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This can be explained like this (note, I'm guessing here, but it seems
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to fit well on the number of T-states).
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  M1:  fetch/decode opcode              4     cycles
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  M2:  tmpL = read(SP)                  3     cycles
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  M3:  ++SP ; tmpH = read(SP)           1+3   cycles
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  M4:  write(SP, H)                     3     cycles
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  M5:  --SP ; write(SP, L) ; HL = tmp   1+3+1 cycles
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  fetching opcode (or prefix) takes 4 cycles in all Z80 instructions
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  reading/writing memory takes 3 cycles on Z80
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This corresponds with order c) [F R0 R1 W1 W0]
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* R800
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On R800, the instruction takes 7 cycles if SP+0 and SP+1 are in the same
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256-byte page, 9 cycles if not (see r800test.txt for more details on this).
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So it seems there are two extra page-breaks in the latter case, order a)
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and d) need only 1 extra page-break (of course it's not impossible there
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still are 2 page-breaks, or one page-break and some other extra cost).
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In any case the timing doesn't give us enough information.
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We need another test to be sure about the order. We'll do this by setting
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the stack pointer to a memory-mapped IO region:
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In the MSXTurboR, in slot 3-3, there's a ROM mapper. Writes to the region
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0x6C00-0x6FFF will switch the ROM in region 0x6000-0x7FFF. The content
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of the ROM is like this:
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  page 0, address 0x6C80/0x6C81: F6 50
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       1                         C3 3E
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       2                         08 07
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Now execute the following program, with slot 3-3 selected in page 1
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(0x4000-0x7FFF).
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-------------------------------
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	org	#C000
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	di
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	ld	(save),sp
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	ld	sp,#6C80
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	xor	a
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	ld	(#6C80),a
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	ld	hl,#0201
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	ex	(sp),hl
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	ld	de,(#6C80)
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	ld	sp,(save)
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	ret
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save	dw	0
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------------------------------
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After running this program the registers HL/DE contain these values
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  HL = 50F6
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  DE = 3EC3
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Register DE contains the ROM content after both writes (W0,W1) are done.
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The value of DE comes from ROM page 1, so writing of L=1 (=W0) must come
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after writing of H=2 (=W1).
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Both register H and L contain the content of the initial ROM page
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(page 0), this means both reads are executed before either of the writes.
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This leaves two possibilities:
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  c) F R0 R1 W1 W0     [FRrww] [FRRwW]
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  e) F R1 R0 W1 W0     [FRrww] [FRRWW]
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I've also indicated the page-breaks when SP+0 and SP+1 are in the same or
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in a different page (again see r800test.txt for details). Possibility e)
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would require 10 cycles, possibility c) matches the measurement of 9
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cycles.
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* conclusion
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Both Z80 and R800 use the same order [F R0 R1 W1 W0]. The result on R800
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is based on measurements, for Z80 it's based on extrapolating T-state
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documentation. It would be nice to also actually measure it on Z80.
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The order [F R0 WO R1 W1] would have been better on R800: it would only
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require 8 cycles in case of a SP+0 SP+1 page break. Though that would be
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incompatible with Z80. Also most of the time it doesn't matter because
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the top-stack-word doesn't cross a page boundary too often (even never
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when the stack is two-bytes aligned).