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◆ main openmsx / src / MSXToshibaTcx200x.cc
3.7 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
e8555c89 Andy McCall 1 
#include "MSXToshibaTcx200x.hh"
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#include "CacheLine.hh"
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#include "serialize.hh"
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namespace openmsx {
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// 7FFF is mapper control register
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//
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// x11xxxxx select SRAM in page 2 (8000H-87FFH, or perhaps mirrored in page 2), R/W
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// x00xxxxx select ROM in page 2, R/W
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// xxxxxx00 select ROM segment 0 in page 2 (screen copy, japanese word processor), R/W
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// xxxxxx01 select ROM segment 1 in page 2 (japanese word processor), R/W
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// xxxxxx10 select ROM segment 2 in page 2 (european word processor), R/W
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// xxxxxx11 select ROM segment 3 in page 2 (japanese word processor), R/W
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// kxxxxxxx COPY key, 0 is pressed (R)
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// b6,b5 = SRAM select. Only pattern 00 and 11 are used, not sure what pattern 01 and 10 do
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// Assumption that SRAM is only visible in page 2, because the ROM segment
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// select is also for page 2 only
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MSXToshibaTcx200x::MSXToshibaTcx200x(DeviceConfig& config)
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	: MSXDevice(config)
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	, rs232Rom(getName() + " RS232C ROM", "rom", config, "rs232")
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	, wordProcessorRom(getName() + " Word Processor ROM", "rom", config, "wordpro")
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	, sram(getName() + " SRAM", 0x800, config)
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	, copyButtonPressed(getCommandController(), "copy_button_pressed",
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                "pressed status of the COPY button", false)
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{
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	reset(EmuTime::dummy());
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}
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void MSXToshibaTcx200x::reset(EmuTime time)
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{
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	copyButtonPressed.setBoolean(false);
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	writeMem(0x7FFF, 0, time);
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}
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bool MSXToshibaTcx200x::sramEnabled() const
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{
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	return (controlReg & 0b0110'0000) == 0b0110'0000;
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	// note: we don't know what the hardware does if only one bit is on 1
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}
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byte MSXToshibaTcx200x::getSelectedSegment() const
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{
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	return controlReg & 0b0000'0011;
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}
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byte MSXToshibaTcx200x::peekMem(uint16_t address, EmuTime /*time*/) const
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{
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	if (address == 0x7FFF) {
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		return byte(controlReg | ((copyButtonPressed.getBoolean() ? 0 : 1) << 7));
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	} else if ((0x4000 <= address) && (address < 0x7FFF)) {
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		return rs232Rom[address - 0x4000];
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	} else if ((0x8000 <= address) && (address < 0xC000)) {
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		if (sramEnabled()) {
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			// TODO: assuming SRAM mirrors all over page 2. Not verified!
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			return sram[address & (sram.size() - 1)];
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		} else {
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			return wordProcessorRom[(address - 0x8000) + getSelectedSegment() * 0x4000];
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		}
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	} else {
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		return 0xFF;
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	}
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}
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byte MSXToshibaTcx200x::readMem(uint16_t address, EmuTime time)
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{
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	return peekMem(address, time);
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}
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void MSXToshibaTcx200x::writeMem(uint16_t address, byte value, EmuTime /*time*/)
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{
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	if (address == 0x7FFF) {
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		controlReg = value & 0b0110'0011; // TODO which bits can be read back?
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		invalidateDeviceRWCache(0x8000, 0x4000);
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	} else if ((0x8000 <= address) && (address < 0xC000) && sramEnabled()) {
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		sram.write(address & (sram.size() - 1), value);
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	}
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}
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const byte* MSXToshibaTcx200x::getReadCacheLine(uint16_t start) const
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{
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	if ((start & CacheLine::HIGH) == (0x7FFF & CacheLine::HIGH)) {
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		return nullptr;
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	} else if ((0x4000 <= start) && (start < 0x7FFF)) {
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		return &rs232Rom[start - 0x4000];
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	} else if ((0x8000 <= start) && (start < 0xC000)) {
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		if (sramEnabled()) {
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			return &sram[start & (sram.size() - 1)];
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		} else {
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			return &wordProcessorRom[(start - 0x8000) + getSelectedSegment() * 0x4000];
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		}
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	}
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	return unmappedRead.data();
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}
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byte* MSXToshibaTcx200x::getWriteCacheLine(uint16_t start)
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{
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	if ((start & CacheLine::HIGH) == (0x7FFF & CacheLine::HIGH)) {
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		return nullptr;
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	} else if ((0x8000 <= start) && (start < 0xC000) && sramEnabled()) {
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		return nullptr;
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	} else {
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		return unmappedWrite.data();
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	}
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}
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template<typename Archive>
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void MSXToshibaTcx200x::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<MSXDevice>(*this);
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	ar.serialize("sram", sram,
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	             "controlReg", controlReg);
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}
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INSTANTIATE_SERIALIZE_METHODS(MSXToshibaTcx200x);
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REGISTER_MSXDEVICE(MSXToshibaTcx200x, "ToshibaTcx200x");
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} // namespace openmsx