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4.8 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
e8555c89 Andy McCall 1 
/*
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 * MEGA-SCSI and ESE-RAM cartridge:
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 *  The mapping does SRAM and MB89352A(MEGA-SCSI) to ASCII8 or
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 *  an interchangeable bank controller.
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 *
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 * Specification:
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 *  SRAM(MegaROM) controller: ASCII8 type
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 *  SRAM capacity           : 128, 256, 512 and 1024KB
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 *  SCSI Protocol Controller: Fujitsu MB89352A
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 *
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 * Bank changing address:
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 *  bank 4(0x4000-0x5fff): 0x6000 - 0x67FF (0x6000 used)
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 *  bank 6(0x6000-0x7fff): 0x6800 - 0x6FFF (0x6800 used)
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 *  bank 8(0x8000-0x9fff): 0x7000 - 0x77FF (0x7000 used)
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 *  bank A(0xa000-0xbfff): 0x7800 - 0x7FFF (0x7800 used)
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 *
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 * ESE-RAM Bank Map:
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 *  BANK 0x00-0x7F (read only)
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 *  BANK 0x80-0xFF (write and read. mirror of 0x00-0x7F)
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 *
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 * MEGA-SCSI Bank Map:
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 *  BANK 0x00-0x3F (sram read only. mirror of 0x80-0xBF)
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 *  BANK 0x40-0x7E (mirror of 0x7F. Use is prohibited)
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 *  BANK 0x7F      (SPC)
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 *  BANK 0x80-0xFF (sram write and read)
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 *
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 * SPC Bank:
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 *  0x0000 - 0x0FFF :
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 *      SPC Data register r/w (mirror of all 0x1FFA)
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 *  0x1000 - 0x1FEF :
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 *      mirror of 0x1FF0 - 0x1FFF
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 *      Use is prohibited about the image
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 *  0x1FF0 - 0x1FFE :
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 *      SPC register
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 *  0x1FFF :
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 *      un mapped
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 *
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 * Note:
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 *  It is possible to access it by putting it out to 0x8000 - 0xBFFF
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 *  though the SPC bank is arranged in chiefly 0x4000-0x5FFF.
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 */
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#include "MegaSCSI.hh"
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#include "MSXException.hh"
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#include "narrow.hh"
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#include "one_of.hh"
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#include "serialize.hh"
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#include "xrange.hh"
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#include <cassert>
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namespace openmsx {
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static constexpr byte SPC = 0x7F;
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size_t MegaSCSI::getSramSize() const
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{
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	size_t sramSize = getDeviceConfig().getChildDataAsInt("sramsize", 1024); // size in kb
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	if (sramSize != one_of(1024u, 512u, 256u, 128u)) {
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		throw MSXException(
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			"SRAM size for ", getName(),
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			" should be 128, 256, 512 or 1024kB and not ",
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			sramSize, "kB!");
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	}
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	return sramSize * 1024; // in bytes
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}
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MegaSCSI::MegaSCSI(DeviceConfig& config)
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	: MSXDevice(config)
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	, mb89352(config)
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	, sram(getName() + " SRAM", getSramSize(), config)
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	, romBlockDebug(*this, mapped, 0x4000, 0x8000, 13)
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	, blockMask(narrow<byte>((sram.size() / 0x2000) - 1))
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{
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	reset(EmuTime::dummy());
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}
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void MegaSCSI::reset(EmuTime /*time*/)
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{
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	for (auto i : xrange(4)) {
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		setSRAM(i, 0);
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	}
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	mb89352.reset(true);
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}
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byte MegaSCSI::readMem(uint16_t address, EmuTime /*time*/)
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{
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	if ((0x4000 <= address) && (address < 0xC000)) {
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		unsigned page = (address / 0x2000) - 2;
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		uint16_t addr = address & 0x1FFF;
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		if (mapped[page] == SPC) {
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			// SPC read
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			if (addr < 0x1000) {
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				// Data Register
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				return mb89352.readDREG();
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			} else {
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				return mb89352.readRegister(addr & 0x0F);
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			}
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		} else {
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			return sram[0x2000 * mapped[page] + addr];
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		}
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	} else {
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		return 0xFF;
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	}
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}
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byte MegaSCSI::peekMem(uint16_t address, EmuTime /*time*/) const
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{
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	if (const byte* cacheline = MegaSCSI::getReadCacheLine(address)) {
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		return *cacheline;
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	} else {
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		address &= 0x1FFF;
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		if (address < 0x1000) {
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			return mb89352.peekDREG();
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		} else {
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			return mb89352.peekRegister(address & 0x0F);
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		}
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	}
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}
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const byte* MegaSCSI::getReadCacheLine(uint16_t address) const
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{
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	if ((0x4000 <= address) && (address < 0xC000)) {
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		unsigned page = (address / 0x2000) - 2;
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		address &= 0x1FFF;
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		if (mapped[page] == SPC) {
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			return nullptr;
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		} else {
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			return &sram[0x2000 * mapped[page] + address];
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		}
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	} else {
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		return unmappedRead.data();
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	}
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}
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void MegaSCSI::writeMem(uint16_t address, byte value, EmuTime /*time*/)
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{
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	if ((0x6000 <= address) && (address < 0x8000)) {
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		byte region = ((address >> 11) & 3);
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		setSRAM(region, value);
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	} else if ((0x4000 <= address) && (address < 0xC000)) {
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		unsigned page = (address / 0x2000) - 2;
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		address &= 0x1FFF;
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		if (mapped[page] == SPC) {
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			if (address < 0x1000) {
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				mb89352.writeDREG(value);
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			} else {
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				mb89352.writeRegister(address & 0x0F, value);
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			}
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		} else if (isWriteable[page]) {
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			sram.write(0x2000 * mapped[page] + address, value);
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		}
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	}
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}
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byte* MegaSCSI::getWriteCacheLine(uint16_t address)
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{
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	if ((0x6000 <= address) && (address < 0x8000)) {
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		return nullptr;
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	} else if ((0x4000 <= address) && (address < 0xC000)) {
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		unsigned page = (address / 0x2000) - 2;
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		if (mapped[page] == SPC) {
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			return nullptr;
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		} else if (isWriteable[page]) {
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			return nullptr;
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		}
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	}
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	return unmappedWrite.data();
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}
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void MegaSCSI::setSRAM(unsigned region, byte block)
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{
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	invalidateDeviceRWCache(region * 0x2000 + 0x4000, 0x2000);
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	assert(region < 4);
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	isWriteable[region] = (block & 0x80) != 0;
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	mapped[region] = ((block & 0xC0) == 0x40) ? 0x7F : (block & blockMask);
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}
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template<typename Archive>
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void MegaSCSI::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.serialize("SRAM",        sram,
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	             "MB89352",     mb89352,
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	             "isWriteable", isWriteable,
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	             "mapped",      mapped);
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}
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INSTANTIATE_SERIALIZE_METHODS(MegaSCSI);
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REGISTER_MSXDEVICE(MegaSCSI, "MegaSCSI");
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} // namespace openmsx