src/serial/MC6850.cc at main · doomsdayone/openmsx

◆ main openmsx / src / serial / MC6850.cc

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#include "MC6850.hh"

#include "MidiInDevice.hh"

#include "EmuTime.hh"
#include "MSXMotherBoard.hh"
#include "serialize.hh"

#include <array>

namespace openmsx {

// control register bits
static constexpr unsigned CR_CDS1 = 0x01; // Counter Divide Select 1
static constexpr unsigned CR_CDS2 = 0x02; // Counter Divide Select 2
static constexpr unsigned CR_CDS  = CR_CDS1 | CR_CDS2;
static constexpr unsigned CR_MR   = CR_CDS1 | CR_CDS2; // Master Reset
// CDS2 CDS1
// 0    0     divide by 1
// 0    1     divide by 16
// 1    0     divide by 64
// 1    1     master reset (!)

static constexpr unsigned CR_WS1  = 0x04; // Word Select 1 (mostly parity)
static constexpr unsigned CR_WS2  = 0x08; // Word Select 2 (mostly nof stop bits)
static constexpr unsigned CR_WS3  = 0x10; // Word Select 3: 7/8 bits
static constexpr unsigned CR_WS   = CR_WS1 | CR_WS2 | CR_WS3; // Word Select
// WS3 WS2 WS1
// 0   0   0   7 bits - 2 stop bits - Even parity
// 0   0   1   7 bits - 2 stop bits - Odd  parity
// 0   1   0   7 bits - 1 stop bit  - Even parity
// 0   1   1   7 bits - 1 stop bit  - Odd  Parity
// 1   0   0   8 bits - 2 stop bits - No   Parity
// 1   0   1   8 bits - 1 stop bit  - No   Parity
// 1   1   0   8 bits - 1 stop bit  - Even parity
// 1   1   1   8 bits - 1 stop bit  - Odd  parity

static constexpr unsigned CR_TC1  = 0x20; // Transmit Control 1
static constexpr unsigned CR_TC2  = 0x40; // Transmit Control 2
static constexpr unsigned CR_TC   = CR_TC1 | CR_TC2; // Transmit Control
// TC2 TC1
// 0   0   /RTS low,  Transmitting Interrupt disabled
// 0   1   /RTS low,  Transmitting Interrupt enabled
// 1   0   /RTS high, Transmitting Interrupt disabled
// 1   1   /RTS low,  Transmits a Break level on the Transmit Data Output.
//                                 Interrupt disabled

static constexpr unsigned CR_RIE  = 0x80; // Receive Interrupt Enable: interrupt
// at Receive Data Register Full, Overrun, low-to-high transition on the Data
// Carrier Detect (/DCD) signal line

// status register bits
static constexpr unsigned STAT_RDRF = 0x01; // Receive Data Register Full
static constexpr unsigned STAT_TDRE = 0x02; // Transmit Data Register Empty
static constexpr unsigned STAT_DCD  = 0x04; // Data Carrier Detect (/DCD)
static constexpr unsigned STAT_CTS  = 0x08; // Clear-to-Send (/CTS)
static constexpr unsigned STAT_FE   = 0x10; // Framing Error
static constexpr unsigned STAT_OVRN = 0x20; // Receiver Overrun
static constexpr unsigned STAT_PE   = 0x40; // Parity Error
static constexpr unsigned STAT_IRQ  = 0x80; // Interrupt Request (/IRQ)

MC6850::MC6850(const std::string& name_, MSXMotherBoard& motherBoard, unsigned clockFreq_)
	: MidiInConnector(motherBoard.getPluggingController(), name_ + "-in")
	, syncRecv (motherBoard.getScheduler())
	, syncTrans(motherBoard.getScheduler())
	, clockFreq(clockFreq_)
	, rxIRQ(motherBoard, name_ + "-rx-IRQ")
	, txIRQ(motherBoard, name_ + "-tx-IRQ")
	, outConnector(motherBoard.getPluggingController(), name_ + "-out")
{
	reset(EmuTime::zero());
	setDataFormat();
}

// (Re-)initialize chip to default values (Tx and Rx disabled)
void MC6850::reset(EmuTime time)
{
	syncRecv .removeSyncPoint();
	syncTrans.removeSyncPoint();
	txClock.reset(time);
	txClock.setFreq(clockFreq);
	rxIRQ.reset();
	txIRQ.reset();
	rxReady = false;
	txShiftRegValid = false;
	pendingOVRN = false;
	controlReg = CR_MR;
	statusReg = 0;
	rxDataReg = 0;
	setDataFormat();
}

uint8_t MC6850::readStatusReg() const
{
	return peekStatusReg();
}

uint8_t MC6850::peekStatusReg() const
{
	uint8_t result = statusReg;
	if (rxIRQ.getState() || txIRQ.getState()) result |= STAT_IRQ;
	return result;
}

uint8_t MC6850::readDataReg()
{
	uint8_t result = peekDataReg();
	statusReg &= uint8_t(~(STAT_RDRF | STAT_OVRN));
	if (pendingOVRN) {
		pendingOVRN = false;
		statusReg |= STAT_OVRN;
	}
	rxIRQ.reset();
	return result;
}

uint8_t MC6850::peekDataReg() const
{
	return rxDataReg;
}

void MC6850::writeControlReg(uint8_t value, EmuTime time)
{
	uint8_t diff = value ^ controlReg;
	if (diff & CR_CDS) {
		if ((value & CR_CDS) == CR_MR) {
			reset(time);
		} else {
			// we got out of MR state
			rxReady = true;
			statusReg |= STAT_TDRE;

			txClock.reset(time);
			switch (value & CR_CDS) {
			case 0: txClock.setFreq(clockFreq,  1); break;
			case 1: txClock.setFreq(clockFreq, 16); break;
			case 2: txClock.setFreq(clockFreq, 64); break;
			}
		}
	}

	controlReg = value;
	if (diff & CR_WS) setDataFormat();

	// update IRQ status
	rxIRQ.set(( value & CR_RIE) && (statusReg & STAT_RDRF));
	txIRQ.set(((value & CR_TC) == 0x20) && (statusReg & STAT_TDRE));
}

// Sync data-format related parameters with the current value of controlReg
void MC6850::setDataFormat()
{
	outConnector.setDataBits(controlReg & CR_WS3 ? DataBits::D8 : DataBits::D7);

	static constexpr std::array<StopBits, 8> stopBits = {
		StopBits::S2, StopBits::S2, StopBits::S1, StopBits::S1,
		StopBits::S2, StopBits::S1, StopBits::S1, StopBits::S1,
	};
	outConnector.setStopBits(stopBits[(controlReg & CR_WS) >> 2]);

	outConnector.setParityBit(
		(controlReg & (CR_WS3 | CR_WS2)) != 0x10, // enable
		(controlReg & CR_WS1) ? Parity::ODD : Parity::EVEN);

	// start-bits, data-bits, parity-bits, stop-bits
	static constexpr std::array<uint8_t, 8> len = {
		1 + 7 + 1 + 2,
		1 + 7 + 1 + 2,
		1 + 7 + 1 + 1,
		1 + 7 + 1 + 1,
		1 + 8 + 0 + 2,
		1 + 8 + 0 + 1,
		1 + 8 + 1 + 1,
		1 + 8 + 1 + 1,
	};
	charLen = len[(controlReg & CR_WS) >> 2];
}

void MC6850::writeDataReg(uint8_t value, EmuTime time)
{
	if ((controlReg & CR_CDS) == CR_MR) return;

	txDataReg = value;
	statusReg &= uint8_t(~STAT_TDRE);
	txIRQ.reset();

	if (syncTrans.isPending()) {
		// We're still sending the previous character, only
		// buffer this one. Don't accept any further characters
	} else {
		// We were not yet sending. Start sending at the next txClock.
		// Important: till that time TDRE should go low
		//  (MC6850 detection routine in Synthesix depends on this)
		txClock.advance(time); // clock edge before or at 'time'
		txClock += 1; // clock edge strictly after 'time'
		syncTrans.setSyncPoint(txClock.getTime());
	}
}

// Triggered between transmitted characters, including before the first and
// after the last character.
void MC6850::execTrans(EmuTime time)
{
	assert(txClock.getTime() == time);
	assert((controlReg & CR_CDS) != CR_MR);

	if (txShiftRegValid) {
		txShiftRegValid = false;
		outConnector.recvByte(txShiftReg, time);
	}

	if (statusReg & STAT_TDRE) {
		// No next character to send, we're done.
	} else {
		// There already is a next character, start sending that now
		// and accept a next one.
		statusReg |= STAT_TDRE;
		if ((controlReg & CR_TC) == 0x20) txIRQ.set();

		txShiftReg = txDataReg;
		txShiftRegValid = true;

		txClock += charLen;
		syncTrans.setSyncPoint(txClock.getTime());
	}
}

// MidiInConnector sends a new character.
void MC6850::recvByte(uint8_t value, EmuTime time)
{
	assert(acceptsData() && ready());

	if (statusReg & STAT_RDRF) {
		// So, there is a byte that has to be read by the MSX still!
		// This happens when the MSX program doesn't
		// respond fast enough to an earlier received byte.
		// The STAT_OVRN flag only becomes active once the prior valid
		// character has been read from the data register.
		pendingOVRN = true;
	} else {
		rxDataReg = value;
		statusReg |= STAT_RDRF;
	}
	// both for OVRN and RDRF an IRQ is raised
	if (controlReg & CR_RIE) rxIRQ.set();

	// Not ready now, but we will be in a while
	rxReady = false;

	// The MC6850 has separate TxCLK and RxCLK inputs, but both share a
	// common divider. This implementation hard-codes an input frequency
	// for both. Below we want the receive clock period, but it's OK
	// to calculate that as 'txClock.getPeriod()'.
	syncRecv.setSyncPoint(time + txClock.getPeriod() * charLen);
}

// Triggered when we're ready to receive the next character.
void MC6850::execRecv(EmuTime time)
{
	assert(acceptsData());
	assert(!rxReady);
	rxReady = true;
	getPluggedMidiInDev().signal(time); // trigger (possible) send of next char
}

// MidiInDevice queries whether it can send a new character 'now'.
bool MC6850::ready()
{
	return rxReady;
}

// MidiInDevice queries whether it can send characters at all.
bool MC6850::acceptsData()
{
	return (controlReg & CR_CDS) != CR_MR;
}

// MidiInDevice informs us about the format of the data it will send
// (MIDI is always 1 start-bit, 8 data-bits, 1 stop-bit, no parity-bits).
void  MC6850::setDataBits(DataBits /*bits*/)
{
	// ignore
}
void MC6850::setStopBits(StopBits /*bits*/)
{
	// ignore
}
void MC6850::setParityBit(bool /*enable*/, Parity /*parity*/)
{
	// ignore
}

// version 1: initial version
// version 2: added control
// version 3: actually working MC6850 with many more member variables
template<typename Archive>
void MC6850::serialize(Archive& ar, unsigned version)
{
	if (ar.versionAtLeast(version, 3)) {
		ar.template serializeBase<MidiInConnector>(*this);
		ar.serialize("outConnector", outConnector,

		             "syncRecv",  syncRecv,
		             "syncTrans", syncTrans,

		             "txClock", txClock,
		             "rxIRQ", rxIRQ,
		             "txIRQ", txIRQ,

		             "rxReady",         rxReady,
		             "txShiftRegValid", txShiftRegValid,
		             "pendingOVRN",     pendingOVRN,

		             "rxDataReg",  rxDataReg,
		             "txDataReg",  txDataReg,
		             "txShiftReg", txShiftReg,
		             "controlReg", controlReg,
		             "statusReg",  statusReg);
	} else if (ar.versionAtLeast(version, 2)) {
		ar.serialize("control", controlReg);
	} else {
		controlReg = 3;
	}

	if constexpr (Archive::IS_LOADER) {
		setDataFormat();
	}
}
INSTANTIATE_SERIALIZE_METHODS(MC6850);

} // namespace openmsx

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1	#include "MC6850.hh"
2
3	#include "MidiInDevice.hh"
4
5	#include "EmuTime.hh"
6	#include "MSXMotherBoard.hh"
7	#include "serialize.hh"
8
9	#include <array>
10
11	namespace openmsx {
12
13	// control register bits
14	static constexpr unsigned CR_CDS1 = 0x01; // Counter Divide Select 1
15	static constexpr unsigned CR_CDS2 = 0x02; // Counter Divide Select 2
16	static constexpr unsigned CR_CDS = CR_CDS1 \| CR_CDS2;
17	static constexpr unsigned CR_MR = CR_CDS1 \| CR_CDS2; // Master Reset
18	// CDS2 CDS1
19	// 0 0 divide by 1
20	// 0 1 divide by 16
21	// 1 0 divide by 64
22	// 1 1 master reset (!)
23
24	static constexpr unsigned CR_WS1 = 0x04; // Word Select 1 (mostly parity)
25	static constexpr unsigned CR_WS2 = 0x08; // Word Select 2 (mostly nof stop bits)
26	static constexpr unsigned CR_WS3 = 0x10; // Word Select 3: 7/8 bits
27	static constexpr unsigned CR_WS = CR_WS1 \| CR_WS2 \| CR_WS3; // Word Select
28	// WS3 WS2 WS1
29	// 0 0 0 7 bits - 2 stop bits - Even parity
30	// 0 0 1 7 bits - 2 stop bits - Odd parity
31	// 0 1 0 7 bits - 1 stop bit - Even parity
32	// 0 1 1 7 bits - 1 stop bit - Odd Parity
33	// 1 0 0 8 bits - 2 stop bits - No Parity
34	// 1 0 1 8 bits - 1 stop bit - No Parity
35	// 1 1 0 8 bits - 1 stop bit - Even parity
36	// 1 1 1 8 bits - 1 stop bit - Odd parity
37
38	static constexpr unsigned CR_TC1 = 0x20; // Transmit Control 1
39	static constexpr unsigned CR_TC2 = 0x40; // Transmit Control 2
40	static constexpr unsigned CR_TC = CR_TC1 \| CR_TC2; // Transmit Control
41	// TC2 TC1
42	// 0 0 /RTS low, Transmitting Interrupt disabled
43	// 0 1 /RTS low, Transmitting Interrupt enabled
44	// 1 0 /RTS high, Transmitting Interrupt disabled
45	// 1 1 /RTS low, Transmits a Break level on the Transmit Data Output.
46	// Interrupt disabled
47
48	static constexpr unsigned CR_RIE = 0x80; // Receive Interrupt Enable: interrupt
49	// at Receive Data Register Full, Overrun, low-to-high transition on the Data
50	// Carrier Detect (/DCD) signal line
51
52	// status register bits
53	static constexpr unsigned STAT_RDRF = 0x01; // Receive Data Register Full
54	static constexpr unsigned STAT_TDRE = 0x02; // Transmit Data Register Empty
55	static constexpr unsigned STAT_DCD = 0x04; // Data Carrier Detect (/DCD)
56	static constexpr unsigned STAT_CTS = 0x08; // Clear-to-Send (/CTS)
57	static constexpr unsigned STAT_FE = 0x10; // Framing Error
58	static constexpr unsigned STAT_OVRN = 0x20; // Receiver Overrun
59	static constexpr unsigned STAT_PE = 0x40; // Parity Error
60	static constexpr unsigned STAT_IRQ = 0x80; // Interrupt Request (/IRQ)
61
62	MC6850::MC6850(const std::string& name_, MSXMotherBoard& motherBoard, unsigned clockFreq_)
63	: MidiInConnector(motherBoard.getPluggingController(), name_ + "-in")
64	, syncRecv (motherBoard.getScheduler())
65	, syncTrans(motherBoard.getScheduler())
66	, clockFreq(clockFreq_)
67	, rxIRQ(motherBoard, name_ + "-rx-IRQ")
68	, txIRQ(motherBoard, name_ + "-tx-IRQ")
69	, outConnector(motherBoard.getPluggingController(), name_ + "-out")
70	{
71	reset(EmuTime::zero());
72	setDataFormat();
73	}
74
75	// (Re-)initialize chip to default values (Tx and Rx disabled)
76	void MC6850::reset(EmuTime time)
77	{
78	syncRecv .removeSyncPoint();
79	syncTrans.removeSyncPoint();
80	txClock.reset(time);
81	txClock.setFreq(clockFreq);
82	rxIRQ.reset();
83	txIRQ.reset();
84	rxReady = false;
85	txShiftRegValid = false;
86	pendingOVRN = false;
87	controlReg = CR_MR;
88	statusReg = 0;
89	rxDataReg = 0;
90	setDataFormat();
91	}
92
93	uint8_t MC6850::readStatusReg() const
94	{
95	return peekStatusReg();
96	}
97
98	uint8_t MC6850::peekStatusReg() const
99	{
100	uint8_t result = statusReg;
101	if (rxIRQ.getState() \|\| txIRQ.getState()) result \|= STAT_IRQ;
102	return result;
103	}
104
105	uint8_t MC6850::readDataReg()
106	{
107	uint8_t result = peekDataReg();
108	statusReg &= uint8_t(~(STAT_RDRF \| STAT_OVRN));
109	if (pendingOVRN) {
110	pendingOVRN = false;
111	statusReg \|= STAT_OVRN;
112	}
113	rxIRQ.reset();
114	return result;
115	}
116
117	uint8_t MC6850::peekDataReg() const
118	{
119	return rxDataReg;
120	}
121
122	void MC6850::writeControlReg(uint8_t value, EmuTime time)
123	{
124	uint8_t diff = value ^ controlReg;
125	if (diff & CR_CDS) {
126	if ((value & CR_CDS) == CR_MR) {
127	reset(time);
128	} else {
129	// we got out of MR state
130	rxReady = true;
131	statusReg \|= STAT_TDRE;
132
133	txClock.reset(time);
134	switch (value & CR_CDS) {
135	case 0: txClock.setFreq(clockFreq, 1); break;
136	case 1: txClock.setFreq(clockFreq, 16); break;
137	case 2: txClock.setFreq(clockFreq, 64); break;
138	}
139	}
140	}
141
142	controlReg = value;
143	if (diff & CR_WS) setDataFormat();
144
145	// update IRQ status
146	rxIRQ.set(( value & CR_RIE) && (statusReg & STAT_RDRF));
147	txIRQ.set(((value & CR_TC) == 0x20) && (statusReg & STAT_TDRE));
148	}
149
150	// Sync data-format related parameters with the current value of controlReg
151	void MC6850::setDataFormat()
152	{
153	outConnector.setDataBits(controlReg & CR_WS3 ? DataBits::D8 : DataBits::D7);
154
155	static constexpr std::array<StopBits, 8> stopBits = {
156	StopBits::S2, StopBits::S2, StopBits::S1, StopBits::S1,
157	StopBits::S2, StopBits::S1, StopBits::S1, StopBits::S1,
158	};
159	outConnector.setStopBits(stopBits[(controlReg & CR_WS) >> 2]);
160
161	outConnector.setParityBit(
162	(controlReg & (CR_WS3 \| CR_WS2)) != 0x10, // enable
163	(controlReg & CR_WS1) ? Parity::ODD : Parity::EVEN);
164
165	// start-bits, data-bits, parity-bits, stop-bits
166	static constexpr std::array<uint8_t, 8> len = {
167	1 + 7 + 1 + 2,
168	1 + 7 + 1 + 2,
169	1 + 7 + 1 + 1,
170	1 + 7 + 1 + 1,
171	1 + 8 + 0 + 2,
172	1 + 8 + 0 + 1,
173	1 + 8 + 1 + 1,
174	1 + 8 + 1 + 1,
175	};
176	charLen = len[(controlReg & CR_WS) >> 2];
177	}
178
179	void MC6850::writeDataReg(uint8_t value, EmuTime time)
180	{
181	if ((controlReg & CR_CDS) == CR_MR) return;
182
183	txDataReg = value;
184	statusReg &= uint8_t(~STAT_TDRE);
185	txIRQ.reset();
186
187	if (syncTrans.isPending()) {
188	// We're still sending the previous character, only
189	// buffer this one. Don't accept any further characters
190	} else {
191	// We were not yet sending. Start sending at the next txClock.
192	// Important: till that time TDRE should go low
193	// (MC6850 detection routine in Synthesix depends on this)
194	txClock.advance(time); // clock edge before or at 'time'
195	txClock += 1; // clock edge strictly after 'time'
196	syncTrans.setSyncPoint(txClock.getTime());
197	}
198	}
199
200	// Triggered between transmitted characters, including before the first and
201	// after the last character.
202	void MC6850::execTrans(EmuTime time)
203	{
204	assert(txClock.getTime() == time);
205	assert((controlReg & CR_CDS) != CR_MR);
206
207	if (txShiftRegValid) {
208	txShiftRegValid = false;
209	outConnector.recvByte(txShiftReg, time);
210	}
211
212	if (statusReg & STAT_TDRE) {
213	// No next character to send, we're done.
214	} else {
215	// There already is a next character, start sending that now
216	// and accept a next one.
217	statusReg \|= STAT_TDRE;
218	if ((controlReg & CR_TC) == 0x20) txIRQ.set();
219
220	txShiftReg = txDataReg;
221	txShiftRegValid = true;
222
223	txClock += charLen;
224	syncTrans.setSyncPoint(txClock.getTime());
225	}
226	}
227
228	// MidiInConnector sends a new character.
229	void MC6850::recvByte(uint8_t value, EmuTime time)
230	{
231	assert(acceptsData() && ready());
232
233	if (statusReg & STAT_RDRF) {
234	// So, there is a byte that has to be read by the MSX still!
235	// This happens when the MSX program doesn't
236	// respond fast enough to an earlier received byte.
237	// The STAT_OVRN flag only becomes active once the prior valid
238	// character has been read from the data register.
239	pendingOVRN = true;
240	} else {
241	rxDataReg = value;
242	statusReg \|= STAT_RDRF;
243	}
244	// both for OVRN and RDRF an IRQ is raised
245	if (controlReg & CR_RIE) rxIRQ.set();
246
247	// Not ready now, but we will be in a while
248	rxReady = false;
249
250	// The MC6850 has separate TxCLK and RxCLK inputs, but both share a
251	// common divider. This implementation hard-codes an input frequency
252	// for both. Below we want the receive clock period, but it's OK
253	// to calculate that as 'txClock.getPeriod()'.
254	syncRecv.setSyncPoint(time + txClock.getPeriod() * charLen);
255	}
256
257	// Triggered when we're ready to receive the next character.
258	void MC6850::execRecv(EmuTime time)
259	{
260	assert(acceptsData());
261	assert(!rxReady);
262	rxReady = true;
263	getPluggedMidiInDev().signal(time); // trigger (possible) send of next char
264	}
265
266	// MidiInDevice queries whether it can send a new character 'now'.
267	bool MC6850::ready()
268	{
269	return rxReady;
270	}
271
272	// MidiInDevice queries whether it can send characters at all.
273	bool MC6850::acceptsData()
274	{
275	return (controlReg & CR_CDS) != CR_MR;
276	}
277
278	// MidiInDevice informs us about the format of the data it will send
279	// (MIDI is always 1 start-bit, 8 data-bits, 1 stop-bit, no parity-bits).
280	void MC6850::setDataBits(DataBits /bits/)
281	{
282	// ignore
283	}
284	void MC6850::setStopBits(StopBits /bits/)
285	{
286	// ignore
287	}
288	void MC6850::setParityBit(bool /enable/, Parity /parity/)
289	{
290	// ignore
291	}
292
293	// version 1: initial version
294	// version 2: added control
295	// version 3: actually working MC6850 with many more member variables
296	template<typename Archive>
297	void MC6850::serialize(Archive& ar, unsigned version)
298	{
299	if (ar.versionAtLeast(version, 3)) {
300	ar.template serializeBase<MidiInConnector>(*this);
301	ar.serialize("outConnector", outConnector,
302
303	"syncRecv", syncRecv,
304	"syncTrans", syncTrans,
305
306	"txClock", txClock,
307	"rxIRQ", rxIRQ,
308	"txIRQ", txIRQ,
309
310	"rxReady", rxReady,
311	"txShiftRegValid", txShiftRegValid,
312	"pendingOVRN", pendingOVRN,
313
314	"rxDataReg", rxDataReg,
315	"txDataReg", txDataReg,
316	"txShiftReg", txShiftReg,
317	"controlReg", controlReg,
318	"statusReg", statusReg);
319	} else if (ar.versionAtLeast(version, 2)) {
320	ar.serialize("control", controlReg);
321	} else {
322	controlReg = 3;
323	}
324
325	if constexpr (Archive::IS_LOADER) {
326	setDataFormat();
327	}
328	}
329	INSTANTIATE_SERIALIZE_METHODS(MC6850);
330
331	} // namespace openmsx

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