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◆ main openmsx / src / fdc / NationalFDC.cc
3.2 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
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#include "NationalFDC.hh"
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#include "DriveMultiplexer.hh"
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#include "WD2793.hh"
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#include "CacheLine.hh"
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#include "serialize.hh"
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namespace openmsx {
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NationalFDC::NationalFDC(DeviceConfig& config)
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	: WD2793BasedFDC(config)
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{
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	// ROM only visible in 0x0000-0x7FFF by default
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	parseRomVisibility(config, 0x0000, 0x8000);
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}
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byte NationalFDC::readMem(uint16_t address, EmuTime time)
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{
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	switch (address & 0x3FC7) {
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	case 0x3F80:
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		return controller.getStatusReg(time);
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	case 0x3F81:
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		return controller.getTrackReg(time);
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	case 0x3F82:
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		return controller.getSectorReg(time);
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	case 0x3F83:
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		return controller.getDataReg(time);
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	case 0x3F84:
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	case 0x3F85:
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	case 0x3F86:
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	case 0x3F87: {
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		byte value = 0x7F;
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		if (controller.getIRQ(time))  value |=  0x80;
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		if (controller.getDTRQ(time)) value &= ~0x40;
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		return value;
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	}
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	default:
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		return NationalFDC::peekMem(address, time);
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	}
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}
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byte NationalFDC::peekMem(uint16_t address, EmuTime time) const
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{
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	// According to atarulum:
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	//  7FBC        is mirrored in 7FBC - 7FBF
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	//  7FB8 - 7FBF is mirrored in 7F80 - 7FBF
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	switch (address & 0x3FC7) {
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	case 0x3F80:
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		return controller.peekStatusReg(time);
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	case 0x3F81:
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		return controller.peekTrackReg(time);
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	case 0x3F82:
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		return controller.peekSectorReg(time);
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	case 0x3F83:
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		return controller.peekDataReg(time);
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	case 0x3F84:
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	case 0x3F85:
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	case 0x3F86:
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	case 0x3F87: {
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		// Drive control IRQ and DRQ lines are not connected to Z80 interrupt request
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		// bit 7: intrq
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		// bit 6: !dtrq
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		// other bits read 1
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		byte value = 0x7F;
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		if (controller.peekIRQ(time))  value |=  0x80;
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		if (controller.peekDTRQ(time)) value &= ~0x40;
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		return value;
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	}
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	default:
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		return MSXFDC::peekMem(address, time);
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	}
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}
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const byte* NationalFDC::getReadCacheLine(uint16_t start) const
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{
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	if ((start & 0x3FC0 & CacheLine::HIGH) == (0x3F80 & CacheLine::HIGH)) {
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		// FDC at 0x7FB8-0x7FBC (also mirrored)
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		return nullptr;
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	} else {
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		return MSXFDC::getReadCacheLine(start);
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	}
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}
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void NationalFDC::writeMem(uint16_t address, byte value, EmuTime time)
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{
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	switch (address & 0x3FC7) {
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	case 0x3F80:
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		controller.setCommandReg(value, time);
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		break;
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	case 0x3F81:
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		controller.setTrackReg(value, time);
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		break;
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	case 0x3F82:
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		controller.setSectorReg(value, time);
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		break;
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	case 0x3F83:
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		controller.setDataReg(value, time);
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		break;
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	case 0x3F84:
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	case 0x3F85:
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	case 0x3F86:
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	case 0x3F87:
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		// bit 0 -> select drive 0
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		// bit 1 -> select drive 1
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		// bit 2 -> side select
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		// bit 3 -> motor on
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		auto drive = [&] {
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			switch (value & 3) {
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				case 1:  return DriveMultiplexer::Drive::A;
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				case 2:  return DriveMultiplexer::Drive::B;
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				default: return DriveMultiplexer::Drive::NONE;
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			}
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		}();
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		multiplexer.selectDrive(drive, time);
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		multiplexer.setSide((value & 0x04) != 0);
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		multiplexer.setMotor((value & 0x08) != 0, time);
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		break;
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	}
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}
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byte* NationalFDC::getWriteCacheLine(uint16_t address)
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{
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	if ((address & 0x3FC0) == (0x3F80 & CacheLine::HIGH)) {
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		// FDC at 0x7FB8-0x7FBC (also mirrored)
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		return nullptr;
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	} else {
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		return unmappedWrite.data();
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	}
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}
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template<typename Archive>
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void NationalFDC::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<WD2793BasedFDC>(*this);
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}
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INSTANTIATE_SERIALIZE_METHODS(NationalFDC);
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REGISTER_MSXDEVICE(NationalFDC, "NationalFDC");
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} // namespace openmsx