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◆ main openmsx / src / fdc / CanonFDC.cc
3.7 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
e8555c89 Andy McCall 1 
#include "CanonFDC.hh"
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#include "CacheLine.hh"
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#include "serialize.hh"
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// Technical info and discussion on:
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//    https://www.msx.org/forum/msx-talk/hardware/canon-v-30f-msx2?page=8
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//
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// 0x7FF8: MB8877A command register (W) / Status register (R)
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// 0x7FF9: MB8877A track register  (R/W)
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// 0x7FFA: MB8877A sector register (R/W)
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// 0x7FFB: MB8877A data register   (R/W)
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// 0x7FFC: drive control
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//   b1,b0: (R/W) drive select (0 = drive 0, 1 = drive 1, 3 = deselect drive)
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//   b2:    (R/W) side select (0 = side 0, 1 = side 1)
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//   b3:    (R/W) motor on (1 = motor on)
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//   b4:     (R)  disk changed (0 = changed)
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//   b5      (R)  some sort of ready (1 = ready)
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//   b6      (R)  DRQ (1 = DRQ)
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//   b7      (R)  IRQ (1 = IRQ)
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// Hardware registers are also visible in page 2 (0xBFF8-0xBFFC).
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namespace openmsx {
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CanonFDC::CanonFDC(DeviceConfig& config)
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	: WD2793BasedFDC(config)
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{
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	reset(getCurrentTime());
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}
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void CanonFDC::reset(EmuTime time)
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{
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	WD2793BasedFDC::reset(time);
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	writeMem(0x3FFC, 0, time);
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}
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byte CanonFDC::readMem(uint16_t address, EmuTime time)
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{
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	switch (address & 0x3FFF) {
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	case 0x3FF8:
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		return controller.getStatusReg(time);
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	case 0x3FF9:
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		return controller.getTrackReg(time);
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	case 0x3FFA:
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		return controller.getSectorReg(time);
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	case 0x3FFB:
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		return controller.getDataReg(time);
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	case 0x3FFC: {
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		// At address 0x76F4 in the disk ROM bit 5 is checked. If this
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		// bit is 0, the code executes a delay loop. Not sure what that
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		// is for. Some kind of hardware debug feature??
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		byte value = 0x30 | controlReg;
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		if (controller.getIRQ(time))  value |= 0x40;
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		if (controller.getDTRQ(time)) value |= 0x80;
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		if (multiplexer.diskChanged()) value &= ~0x10;
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		return value;
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	}
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	default:
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		return CanonFDC::peekMem(address, time);
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	}
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}
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byte CanonFDC::peekMem(uint16_t address, EmuTime time) const
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{
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	switch (address & 0x3FFF) {
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	case 0x3FF8:
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		return controller.peekStatusReg(time);
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	case 0x3FF9:
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		return controller.peekTrackReg(time);
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	case 0x3FFA:
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		return controller.peekSectorReg(time);
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	case 0x3FFB:
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		return controller.peekDataReg(time);
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	case 0x3FFC: {
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		byte value = 0x30 | controlReg;
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		if (controller.peekIRQ(time))  value |= 0x40;
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		if (controller.peekDTRQ(time)) value |= 0x80;
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		if (multiplexer.peekDiskChanged()) value &= ~0x10;
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		return value;
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	}
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	default:
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		return MSXFDC::peekMem(address, time);
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	}
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}
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const byte* CanonFDC::getReadCacheLine(uint16_t start) const
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{
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	if ((start & 0x3FFF & CacheLine::HIGH) == (0x3FF0 & CacheLine::HIGH)) {
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		// FDC at 0x7FF8-0x7FFC and 0xBFF8-0xBFFC
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		return nullptr;
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	} else {
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		return MSXFDC::getReadCacheLine(start);
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	}
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}
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void CanonFDC::writeMem(uint16_t address, byte value, EmuTime time)
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{
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	switch (address & 0x3FFF) {
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	case 0x3FF8:
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		controller.setCommandReg(value, time);
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		break;
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	case 0x3FF9:
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		controller.setTrackReg(value, time);
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		break;
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	case 0x3FFA:
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		controller.setSectorReg(value, time);
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		break;
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	case 0x3FFB:
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		controller.setDataReg(value, time);
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		break;
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	case 0x3FFC: {
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		controlReg = value & 0x0F;
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		auto drive = [&] {
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			switch (value & 3) {
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			case 0:  return DriveMultiplexer::Drive::A;
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			case 1:  return DriveMultiplexer::Drive::B;
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			default: return DriveMultiplexer::Drive::NONE;
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			}
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		}();
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		multiplexer.selectDrive(drive, time);
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		multiplexer.setSide ((value & 0x04) != 0);
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		multiplexer.setMotor((value & 0x08) != 0, time);
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		break;
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	}
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	}
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}
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byte* CanonFDC::getWriteCacheLine(uint16_t address)
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{
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	if ((address & 0x3FFF & CacheLine::HIGH) == (0x3FF0 & CacheLine::HIGH)) {
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		return nullptr;
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	} else {
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		return unmappedWrite.data();
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	}
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}
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template<typename Archive>
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void CanonFDC::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<WD2793BasedFDC>(*this);
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	ar.serialize("controlReg", controlReg);
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}
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INSTANTIATE_SERIALIZE_METHODS(CanonFDC);
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REGISTER_MSXDEVICE(CanonFDC, "CanonFDC");
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} // namespace openmsx