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◆ main openmsx / src / fdc / SanyoFDC.cc
3.4 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
e8555c89 Andy McCall 1 
#include "SanyoFDC.hh"
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#include "DriveMultiplexer.hh"
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#include "WD2793.hh"
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#include "CacheLine.hh"
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#include "serialize.hh"
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// Note: although this implementation seems to work (e.g. for the Sanyo
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// MFD-001), it has not been checked on real hardware how the FDC registers are
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// mirrored across the slot, nor how the ROM is visible in the slot. Currently
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// FDC registers are implemented to be not mirrored, and ROM is implemented to
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// be visible in page 0 and 1.
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namespace openmsx {
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SanyoFDC::SanyoFDC(DeviceConfig& config)
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	: WD2793BasedFDC(config)
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{
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	// ROM only visible in 0x0000-0x7FFF by default (not verified!)
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	parseRomVisibility(config, 0x0000, 0x8000);
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}
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byte SanyoFDC::readMem(uint16_t address, EmuTime time)
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{
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	switch (address) {
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	case 0x7FF8:
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		return controller.getStatusReg(time);
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	case 0x7FF9:
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		return controller.getTrackReg(time);
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	case 0x7FFA:
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		return controller.getSectorReg(time);
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	case 0x7FFB:
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		return controller.getDataReg(time);
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	case 0x7FFC:
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	case 0x7FFD:
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	case 0x7FFE:
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	case 0x7FFF: {
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		byte value = 0x3F;
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		if (controller.getIRQ(time))  value |= 0x80;
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		if (controller.getDTRQ(time)) value |= 0x40;
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		return value;
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	}
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	default:
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		return SanyoFDC::peekMem(address, time);
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	}
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}
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byte SanyoFDC::peekMem(uint16_t address, EmuTime time) const
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{
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	switch (address) {
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	case 0x7FF8:
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		return controller.peekStatusReg(time);
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	case 0x7FF9:
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		return controller.peekTrackReg(time);
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	case 0x7FFA:
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		return controller.peekSectorReg(time);
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	case 0x7FFB:
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		return controller.peekDataReg(time);
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	case 0x7FFC:
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	case 0x7FFD:
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	case 0x7FFE:
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	case 0x7FFF: {
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		// Drive control IRQ and DRQ lines are not connected to Z80 interrupt request
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		// bit 7: intrq
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		// bit 6: dtrq
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		// other bits read 1
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		byte value = 0x3F;
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		if (controller.peekIRQ(time))  value |= 0x80;
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		if (controller.peekDTRQ(time)) value |= 0x40;
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		return value;
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	}
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	default:
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		return MSXFDC::peekMem(address, time);
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	}
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}
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const byte* SanyoFDC::getReadCacheLine(uint16_t start) const
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{
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	if ((start & CacheLine::HIGH) == (0x7FF8 & CacheLine::HIGH)) {
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		// FDC at 0x7FF8-0x7FFC - mirroring behaviour unknown
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		return nullptr;
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	} else {
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		return MSXFDC::getReadCacheLine(start);
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	}
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}
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void SanyoFDC::writeMem(uint16_t address, byte value, EmuTime time)
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{
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	switch (address) {
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	case 0x7FF8:
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		controller.setCommandReg(value, time);
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		break;
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	case 0x7FF9:
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		controller.setTrackReg(value, time);
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		break;
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	case 0x7FFA:
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		controller.setSectorReg(value, time);
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		break;
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	case 0x7FFB:
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		controller.setDataReg(value, time);
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		break;
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	case 0x7FFC:
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	case 0x7FFD:
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	case 0x7FFE:
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	case 0x7FFF:
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		// bit 0 -> select drive 0
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		// bit 1 -> select drive 1
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		// bit 2 -> side select
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		// bit 3 -> motor on
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		auto drive = [&] {
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			switch (value & 3) {
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				case 1:  return DriveMultiplexer::Drive::A;
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				case 2:  return DriveMultiplexer::Drive::B;
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				default: return DriveMultiplexer::Drive::NONE;
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			}
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		}();
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		multiplexer.selectDrive(drive, time);
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		multiplexer.setSide((value & 0x04) != 0);
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		multiplexer.setMotor((value & 0x08) != 0, time);
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		break;
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	}
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}
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byte* SanyoFDC::getWriteCacheLine(uint16_t address)
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{
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	if ((address & CacheLine::HIGH) == (0x7FF8 & CacheLine::HIGH)) {
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		// FDC at 0x7FF8-0x7FFC - mirroring behaviour unknown
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		return nullptr;
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	} else {
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		return unmappedWrite.data();
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	}
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}
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template<typename Archive>
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void SanyoFDC::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<WD2793BasedFDC>(*this);
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}
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INSTANTIATE_SERIALIZE_METHODS(SanyoFDC);
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REGISTER_MSXDEVICE(SanyoFDC, "SanyoFDC");
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} // namespace openmsx