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◆ main openmsx / src / sound / SVIPSG.cc
3.7 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
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#include "SVIPSG.hh"
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#include "JoystickPort.hh"
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#include "LedStatus.hh"
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#include "MSXCPUInterface.hh"
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#include "MSXMotherBoard.hh"
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#include "serialize.hh"
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#include "stl.hh"
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//        Slot 0    Slot 1    Slot 2    Slot 3
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// FFFF +---------+---------+---------+---------+
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//      | Bank 2  | Bank 12 | Bank 22 | Bank 32 | Page 3
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//      |   RAM   |ROM Cart |   RAM   |   RAM   |
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// 8000 |00000000 |01010000 |10100000 |11110000 | Page 2
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//      +---------+---------+---------+---------+
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// 7FFF | Bank 1  | Bank 11 | Bank 21 | Bank 31 | Page 1
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//      |ROM BASIC|ROM Cart |   RAM   |   RAM   |
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//      |00000000 |00000101 |00001010 |00001111 | Page 0
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// 0000 +---------+---------+---------+---------+
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//
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// PSG Port A Input
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// Bit Name   Description
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//  0  FWD1   Joystick 1, Forward
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//  1  BACK1  Joystick 1, Back
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//  2  LEFT1  Joystick 1, Left
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//  3  RIGHT1 Joystick 1, Right
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//  4  FWD2   Joystick 2, Forward
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//  5  BACK2  Joystick 2, Back
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//  6  LEFT2  Joystick 2, Left
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//  7  RIGHT2 Joystick 2, Right
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//
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// PSG Port B Output
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// Bit Name    Description
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// 0   /CART   Memory bank 11, ROM 0000-7FFF (cartridge /CCS1, /CCS2)
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// 1   /BK21   Memory bank 21, RAM 0000-7FFF
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// 2   /BK22   Memory bank 22, RAM 8000-FFFF
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// 3   /BK31   Memory bank 31, RAM 0000-7FFF
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// 4   /BK32   Memory bank 32, RAM 8000-7FFF
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// 5   CAPS    Caps-Lock LED
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// 6   /ROMEN0 Memory bank 12, ROM 8000-BFFF* (cartridge /CCS3)
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// 7   /ROMEN1 Memory bank 12, ROM C000-FFFF* (cartridge /CCS4)
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//
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// * The /CART signal must be active for any effect,
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//   then all banks of RAM are disabled.
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namespace openmsx {
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// MSXDevice
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SVIPSG::SVIPSG(const DeviceConfig& config)
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	: MSXDevice(config)
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	, ports(generate_array<2>([&](auto i) { return &getMotherBoard().getJoystickPort(unsigned(i)); }))
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	, ay8910("PSG", *this, config, getCurrentTime())
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{
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	reset(getCurrentTime());
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}
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SVIPSG::~SVIPSG()
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{
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	powerDown(EmuTime::dummy());
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}
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void SVIPSG::reset(EmuTime time)
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{
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	registerLatch = 0;
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	ay8910.reset(time);
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}
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void SVIPSG::powerDown(EmuTime /*time*/)
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{
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	getMotherBoard().getLedStatus().setLed(LedStatus::CAPS, false);
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}
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byte SVIPSG::readIO(uint16_t /*port*/, EmuTime time)
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{
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	return ay8910.readRegister(registerLatch, time);
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}
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byte SVIPSG::peekIO(uint16_t /*port*/, EmuTime time) const
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{
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	return ay8910.peekRegister(registerLatch, time);
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}
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void SVIPSG::writeIO(uint16_t port, byte value, EmuTime time)
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{
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	switch (port & 0x07) {
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	case 0:
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		registerLatch = value & 0x0F;
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		break;
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	case 4:
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		ay8910.writeRegister(registerLatch, value, time);
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		break;
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	}
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}
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// AY8910Periphery
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byte SVIPSG::readA(EmuTime time)
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{
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	return byte(((ports[1]->read(time) & 0x0F) << 4) |
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	            ((ports[0]->read(time) & 0x0F) << 0));
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}
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void SVIPSG::writeB(byte value, EmuTime /*time*/)
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{
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	getMotherBoard().getLedStatus().setLed(LedStatus::CAPS, (value & 0x20) != 0);
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	// Default to bank 1 and 2
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	byte psReg = 0;
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	switch (~value & 0x14) {
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	case 0x04: // bk22
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		psReg = 0xa0;
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		break;
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	case 0x10: // bk32
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		psReg = 0xf0;
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		break;
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	}
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	switch (~value & 0x0B) {
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	case 1: // bk12 (cart)?
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		if ((~value & 0x80) || (~value & 0x40)) {
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			psReg = 0x50;
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		}
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		// bk11 (cart)
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		psReg |= 0x05;
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		break;
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	case 2: // bk21
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		psReg |= 0x0a;
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		break;
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	case 8: // bk31
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		psReg |= 0x0f;
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		break;
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	}
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	getMotherBoard().getCPUInterface().setPrimarySlots(psReg);
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	prev = value;
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}
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template<typename Archive>
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void SVIPSG::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<MSXDevice>(*this);
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	ar.serialize("ay8910",        ay8910,
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	             "registerLatch", registerLatch);
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	byte portB = prev;
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	ar.serialize("portB", portB);
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	if constexpr (Archive::IS_LOADER) {
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		writeB(portB, getCurrentTime());
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	}
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}
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INSTANTIATE_SERIALIZE_METHODS(SVIPSG);
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REGISTER_MSXDEVICE(SVIPSG, "SVI-328 PSG");
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} // namespace openmsx