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◆ main openmsx / src / sound / DalSoRiR2.cc
7.7 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
e8555c89 Andy McCall 1 
#include "DalSoRiR2.hh"
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#include "MSXCPUInterface.hh"
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#include "serialize.hh"
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#include "ranges.hh"
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namespace openmsx {
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// bit(s) of the memory bank selection registers regBank[n]
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static constexpr byte REG_BANK_SEGMENT_MASK = (1 << 5) - 1; // 5-bits
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// bit(s) of the frame selection registers regFrame[n]
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static constexpr byte DISABLE = 1 << 7;
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static constexpr byte REG_FRAME_SEGMENT_MASK = (1 << 3) - 1; // 3-bits
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// bits of the configuration register regCfg
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static constexpr byte ENA_S0 = 1 << 5;
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static constexpr byte ENA_FW = 1 << 4;
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static constexpr byte ENA_C4 = 1 << 1;
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static constexpr byte ENA_C0 = 1 << 0;
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DalSoRiR2::DalSoRiR2(DeviceConfig& config)
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	: MSXDevice(config)
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	, ymf278b(getName(),
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	          size_t(4096 * 1024), // 4MB RAM
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	          config,
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	          [this](bool mode0, std::span<const uint8_t> rom, std::span<const uint8_t> ram,
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	                std::span<YMF278::Block128, 32> memPtrs) {
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		     setupMemPtrs(mode0, rom, ram, memPtrs);
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		  }, getCurrentTime())
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	, sram(config, getName() + " RAM", "DalSoRi R2 RAM", 0x8000)
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	, flash(getName() + " flash", AmdFlashChip::SST39SF010, {}, config, "flash")
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	, dipSwitchBDIS(getCommandController(),
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		getName() + " DIP switch BDIS",
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		"Controls the BDIS DIP switch position. ON = Disable BIOS (flash memory access)", false)
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	, dipSwitchMCFG(getCommandController(),
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		getName() + " DIP switch MCFG",
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		"Controls the MCFG DIP switch position. ON = Enable sample RAM instead of sample ROM on reset.", false)
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	, dipSwitchIO_C0(getCommandController(),
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		getName() + " DIP switch IO/C0",
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		"Controls the IO/C0 DIP switch position. ON = Enable I/O addres C0H~C3H on reset. This is the MSX-AUDIO compatible I/O port range.", true)
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	, dipSwitchIO_C4(getCommandController(),
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		getName() + " DIP switch IO/C4",
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		"Controls the IO/C4 DIP switch position. ON = Enable I/O addres C4H~C7H on reset. This is the MoonSound compatible I/O port range", true)
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	, biosDisable(dipSwitchBDIS.getBoolean())
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{
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	dipSwitchBDIS.attach(*this);
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	powerUp(getCurrentTime());
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}
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DalSoRiR2::~DalSoRiR2()
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{
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	setRegCfg(0); // unregister any FM I/O ports
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	dipSwitchBDIS.detach(*this);
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}
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void DalSoRiR2::setupMemPtrs(
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	bool mode0,
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	std::span<const uint8_t> rom,
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	std::span<const uint8_t> ram,
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	std::span<YMF278::Block128, 32> memPtrs) const
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{
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	// /MCS0: connected to either a 2MB ROM or a 2MB RAM chip (dynamically
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	//        selectable via software)
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	// /MCS1: connected to a 2MB RAM chip
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	// /MCS2../MCS9: unused
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	static constexpr auto k128 = YMF278::k128;
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	// first 2MB, either ROM or RAM, both mode0 and mode1
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	bool enableRam = regCfg & ENA_S0;
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	auto mem0 = enableRam ? std::span<const uint8_t>{ram} : std::span<const uint8_t>{rom};
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	for (auto i : xrange(16)) {
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		memPtrs[i] = subspan<k128>(mem0, i * k128);
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	}
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	// second 2MB
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	if (mode0) [[likely]] {
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		// mode 0: RAM
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		for (auto i : xrange(16, 32)) {
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			memPtrs[i] = subspan<k128>(ram, i * k128);
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		}
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	} else {
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		// mode 1: unmapped (normally shouldn't be used on DalSoRiR2)
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		// Note: in this mode accessing region [0x00'0000, 0x10'0000) activates
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		// both /MCS0 and /MCS1, thus two chips (ROM+RAM or RAM+RAM) get activated
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		// simultaneously. That might cause problems on the real hardware. Here we
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		// emulate it by ignoring the problem, as-if only /MCS0 was active.
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		for (auto i : xrange(16, 32)) {
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			memPtrs[i] = YMF278::Block128{};
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		}
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	}
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}
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void DalSoRiR2::powerUp(EmuTime time)
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{
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	ymf278b.powerUp(time);
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	reset(time);
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}
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void DalSoRiR2::reset(EmuTime time)
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{
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	ymf278b.reset(time);
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	flash.reset();
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	ranges::iota(regBank, byte(0));
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	ranges::iota(regFrame, byte(0));
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	setRegCfg((dipSwitchMCFG. getBoolean() ? ENA_S0 : 0) |
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	          (dipSwitchIO_C0.getBoolean() ? ENA_C0 : 0) |
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	          (dipSwitchIO_C4.getBoolean() ? ENA_C4 : 0));
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}
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void DalSoRiR2::setRegCfg(byte value)
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{
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	auto registerHelper = [this](bool enable, byte base) {
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		if (enable) {
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			getCPUInterface().  register_IO_InOut_range(base, 4, this);
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		} else {
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			getCPUInterface().unregister_IO_InOut_range(base, 4, this);
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		}
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	};
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	if ((value ^ regCfg) & ENA_C0) { // enable C0 changed
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		registerHelper((value & ENA_C0) != 0, 0xC0);
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	}
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	if ((value ^ regCfg) & ENA_C4) { // enable C4 changed
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		registerHelper((value & ENA_C4) != 0, 0xC4);
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	}
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	if ((value ^ regCfg) & ENA_FW) {
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		invalidateDeviceRWCache();
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	}
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	regCfg = value;
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	ymf278b.setupMemoryPointers(); // ENA_S0 might have changed
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}
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byte DalSoRiR2::readIO(uint16_t port, EmuTime time)
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{
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	return ymf278b.readIO(port, time);
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}
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byte DalSoRiR2::peekIO(uint16_t port, EmuTime time) const
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{
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	return ymf278b.peekIO(port, time);
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}
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void DalSoRiR2::writeIO(uint16_t port, byte value, EmuTime time)
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{
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	ymf278b.writeIO(port, value, time);
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}
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std::optional<size_t> DalSoRiR2::getSramAddr(uint16_t addr) const
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{
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	auto get = [&](byte frame) -> size_t {
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		return (addr & 0x0FFF) + (frame & REG_FRAME_SEGMENT_MASK) * 0x1000;
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	};
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	if ((0x3000 <= addr) && (addr < 0x4000)) {
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		// SRAM frame 0
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		return get(0);
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	} else if ((0x7000 <= addr) && (addr < 0x8000) && ((regFrame[0] & DISABLE) == 0)) {
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		// SRAM frame 1
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		return get(regFrame[0]);
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	} else if ((0xB000 <= addr) && (addr < 0xC000) && ((regFrame[1] & DISABLE) == 0)) {
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		// SRAM frame 2
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		return get(regFrame[1]);
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	} else {
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		return {};
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	}
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}
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unsigned DalSoRiR2::getFlashAddr(uint16_t addr) const
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{
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	auto page = addr >> 14;
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	auto bank = regBank[page] & REG_BANK_SEGMENT_MASK;
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	auto offset = addr & 0x3FFF;
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	return 0x4000 * bank + offset;
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}
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byte DalSoRiR2::readMem(uint16_t addr, EmuTime time)
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{
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	if (auto r = getSramAddr(addr)) {
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		return sram[*r];
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	} else if (!biosDisable) {
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		return flash.read(getFlashAddr(addr), time);
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	}
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	return 0xFF;
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}
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byte DalSoRiR2::peekMem(uint16_t addr, EmuTime time) const
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{
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	if (auto r = getSramAddr(addr)) {
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		return sram[*r];
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	} else if (!biosDisable) {
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		return flash.peek(getFlashAddr(addr), time);
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	}
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	return 0xFF;
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}
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const byte* DalSoRiR2::getReadCacheLine(uint16_t start) const
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{
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	if (auto r = getSramAddr(start)) {
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		return &sram[*r];
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	} else if (!biosDisable) {
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		return flash.getReadCacheLine(getFlashAddr(start));
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	}
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	return unmappedRead.data();
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}
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void DalSoRiR2::writeMem(uint16_t addr, byte value, EmuTime time)
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{
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	if (auto r = getSramAddr(addr)) {
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		sram[*r] = value;
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	} else if ((0x6000 <= addr) && (addr < 0x6400)) {
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		auto bank = (addr >> 8) & 3;
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		regBank[bank] = value;
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		invalidateDeviceRWCache(bank * 0x4000, 0x4000);
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	} else if ((0x6500 <= addr) && (addr < 0x6700)) {
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		auto frame = (addr >> 9) & 1; // [0x6500,0x65FF] -> 0, [0x6600,0x66FF] -> 1
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		regFrame[frame] = value;
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		invalidateDeviceRWCache(0x7000 + frame * 0x4000, 0x1000);
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	} else if ((0x6700 <= addr) && (addr < 0x6800)) {
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		setRegCfg(value);
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	} else if (!biosDisable && ((regCfg & ENA_FW) != 0)) {
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		flash.write(getFlashAddr(addr), value, time);
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	}
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}
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byte* DalSoRiR2::getWriteCacheLine(uint16_t start)
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{
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	if (auto r = getSramAddr(start)) {
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		return &sram[*r];
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	} else {
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		// bank/frame/cfg registers or flash, not cacheable
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		return nullptr;
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	}
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}
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void DalSoRiR2::update(const Setting& setting) noexcept
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{
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	assert(&setting == &dipSwitchBDIS); (void)setting;
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	auto newBiosDisable = dipSwitchBDIS.getBoolean();
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	if (biosDisable != newBiosDisable) {
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		biosDisable = newBiosDisable;
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		invalidateDeviceRWCache();
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	}
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}
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// version 1: initial version
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template<typename Archive>
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void DalSoRiR2::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<MSXDevice>(*this);
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	auto backupRegCfg = regCfg;
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	ar.serialize("ymf278b",   ymf278b,
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	             "sram",      sram,
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	             "regBank",   regBank,
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	             "regFrame",  regFrame,
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	             "regCfg",    backupRegCfg);
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	if constexpr (Archive::IS_LOADER) {
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		setRegCfg(backupRegCfg); // register ports and setupMemoryPointers()
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	}
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	// no need to serialize biosDisable
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}
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INSTANTIATE_SERIALIZE_METHODS(DalSoRiR2);
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REGISTER_MSXDEVICE(DalSoRiR2, "DalSoRiR2");
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} // namespace openmsx