| 1 |
#ifndef CHECKEDRAM_HH |
| 2 |
#define CHECKEDRAM_HH |
| 3 |
|
| 4 |
#include "Ram.hh" |
| 5 |
|
| 6 |
#include "CacheLine.hh" |
| 7 |
#include "TclCallback.hh" |
| 8 |
|
| 9 |
#include "Observer.hh" |
| 10 |
|
| 11 |
#include <bitset> |
| 12 |
#include <cstdint> |
| 13 |
#include <vector> |
| 14 |
|
| 15 |
namespace openmsx { |
| 16 |
|
| 17 |
class DeviceConfig; |
| 18 |
class MSXCPU; |
| 19 |
class Setting; |
| 20 |
|
| 21 |
|
| 22 |
|
| 23 |
|
| 24 |
|
| 25 |
|
| 26 |
|
| 27 |
|
| 28 |
|
| 29 |
|
| 30 |
class CheckedRam final : private Observer<Setting> |
| 31 |
{ |
| 32 |
public: |
| 33 |
CheckedRam(const DeviceConfig& config, const std::string& name, |
| 34 |
static_string_view description, size_t size); |
| 35 |
~CheckedRam(); |
| 36 |
|
| 37 |
[[nodiscard]] uint8_t read(size_t addr); |
| 38 |
[[nodiscard]] uint8_t peek(size_t addr) const { return ram[addr]; } |
| 39 |
void write(size_t addr, uint8_t value); |
| 40 |
|
| 41 |
[[nodiscard]] const uint8_t* getReadCacheLine(size_t addr) const; |
| 42 |
[[nodiscard]] uint8_t* getWriteCacheLine(size_t addr); |
| 43 |
[[nodiscard]] uint8_t* getRWCacheLines(size_t addr, size_t size); |
| 44 |
|
| 45 |
[[nodiscard]] size_t size() const { return ram.size(); } |
| 46 |
void clear(); |
| 47 |
|
| 48 |
|
| 49 |
|
| 50 |
|
| 51 |
|
| 52 |
|
| 53 |
|
| 54 |
[[nodiscard]] Ram& getUncheckedRam() { return ram; } |
| 55 |
|
| 56 |
|
| 57 |
|
| 58 |
|
| 59 |
|
| 60 |
private: |
| 61 |
void init(); |
| 62 |
|
| 63 |
|
| 64 |
void update(const Setting& setting) noexcept override; |
| 65 |
|
| 66 |
private: |
| 67 |
std::vector<bool> completely_initialized_cacheline; |
| 68 |
std::vector<std::bitset<CacheLine::SIZE>> uninitialized; |
| 69 |
Ram ram; |
| 70 |
MSXCPU& msxcpu; |
| 71 |
TclCallback umrCallback; |
| 72 |
}; |
| 73 |
|
| 74 |
} |
| 75 |
|
| 76 |
#endif |