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◆ main openmsx / src / memory / MSXMegaRam.cc
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/*
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 * Adriano Camargo Rodrigues da Cunha wrote:
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 *
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 *  Any address inside a 8k page can change the page.  In other
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 *  words:
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 *
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 *  for 4000h-5FFFh, mapping addresses are 4000h-5FFFh
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 *  for 6000h-7FFFh, mapping addresses are 6000h-7FFFh
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 *  for 8000h-9FFFh, mapping addresses are 8000h-9FFFh
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 *  for A000h-BFFFh, mapping addresses are A000h-BFFFh
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 *
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 *  If you do an IN A,(8Eh) (the value of A register is unknown and
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 *  never used) you can write on MegaRAM pages, but you can't map
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 *  pages. If you do an OUT (8Eh),A (the value of A register doesn't
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 *  matter) you can't write to MegaRAM pages, but you can map them.
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 *
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 *  Another thing: the MegaRAMs of Ademir Carchano have a mirror
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 *  effect: if you map the page 0 of MegaRAM slot, you'll be
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 *  accessing the same area of 8000h-BFFFh of this slot; if you map
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 *  the page 3 of MegaRAM slot, you'll be accessing the same area of
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 *  4000h-7FFFh of this slot. I don't know any software that makes
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 *  use of this feature, except UZIX for MSX1.
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 */
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#include "MSXMegaRam.hh"
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#include "DeviceConfig.hh"
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#include "MSXException.hh"
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#include "Rom.hh"
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#include "narrow.hh"
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#include "serialize.hh"
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#include "xrange.hh"
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#include <bit>
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#include <memory>
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namespace openmsx {
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[[nodiscard]] static unsigned getNumBlocks(const DeviceConfig& config)
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{
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	int size = config.getChildDataAsInt("size", 0); // size in kB
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	if (const auto* err = [&] -> const char* {
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		if (size < 0)         return "Cannot be negative.";
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		if (size > (8 * 256)) return "Cannot be larger than 2048.";
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		if ((size % 8) != 0)  return "Must be a multiple of 8.";
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		return nullptr;
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	}()) {
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		throw MSXException("Invalid MegaRam size: ", size, ". ", err);
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	}
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	return size / 8;
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}
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MSXMegaRam::MSXMegaRam(DeviceConfig& config)
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	: MSXDevice(config)
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	, numBlocks(getNumBlocks(config)) // number of 8kB blocks
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	, ram(config, getName() + " RAM", "Mega-RAM", numBlocks * 0x2000)
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	, rom(config.findChild("rom")
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	      ? std::make_unique<Rom>(getName() + " ROM", "Mega-RAM DiskROM", config)
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	      : nullptr)
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	, romBlockDebug(*this, bank, 0x0000, 0x10000, 13, 0, 3)
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	, maskBlocks(narrow<byte>(std::bit_ceil(numBlocks) - 1))
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{
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	powerUp(EmuTime::dummy());
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}
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MSXMegaRam::~MSXMegaRam() = default;
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void MSXMegaRam::powerUp(EmuTime time)
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{
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	for (auto i : xrange(byte(4))) {
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		setBank(i, 0);
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	}
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	writeMode = false;
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	ram.clear();
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	reset(time);
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}
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void MSXMegaRam::reset(EmuTime /*time*/)
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{
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	// selected banks nor writeMode does change after reset
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	romMode = rom != nullptr; // select rom mode if there is a rom
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}
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byte MSXMegaRam::readMem(uint16_t address, EmuTime /*time*/)
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{
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	return *MSXMegaRam::getReadCacheLine(address);
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}
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const byte* MSXMegaRam::getReadCacheLine(uint16_t address) const
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{
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	if (romMode) {
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		if (address >= 0x4000 && address <= 0xBFFF) {
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			return &(*rom)[address - 0x4000];
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		}
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		return unmappedRead.data();
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	}
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	unsigned block = bank[(address & 0x7FFF) / 0x2000];
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	return (block < numBlocks)
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	     ? &ram[(block * 0x2000) + (address & 0x1FFF)]
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	     : unmappedRead.data();
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}
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void MSXMegaRam::writeMem(uint16_t address, byte value, EmuTime /*time*/)
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{
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	if (byte* tmp = getWriteCacheLine(address)) {
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		*tmp = value;
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	} else {
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		assert(!romMode && !writeMode);
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		setBank(narrow<byte>((address & 0x7FFF) / 0x2000), value);
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	}
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}
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byte* MSXMegaRam::getWriteCacheLine(uint16_t address)
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{
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	if (romMode) return unmappedWrite.data();
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	if (writeMode) {
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		unsigned block = bank[(address & 0x7FFF) / 0x2000];
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		return (block < numBlocks)
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		     ? &ram[(block * 0x2000) + (address & 0x1FFF)]
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		     : unmappedWrite.data();
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	} else {
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		return nullptr;
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	}
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}
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byte MSXMegaRam::readIO(uint16_t port, EmuTime /*time*/)
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{
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	switch (port & 1) {
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		case 0:
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			// enable writing
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			writeMode = true;
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			romMode = false;
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			break;
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		case 1:
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			if (rom) romMode = true;
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			break;
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	}
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	invalidateDeviceRWCache();
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	return 0xFF; // return value doesn't matter
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}
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byte MSXMegaRam::peekIO(uint16_t /*port*/, EmuTime /*time*/) const
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{
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	return 0xFF;
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}
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void MSXMegaRam::writeIO(uint16_t port, byte /*value*/, EmuTime /*time*/)
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{
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	switch (port & 1) {
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		case 0:
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			// enable switching
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			writeMode = false;
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			romMode = false;
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			break;
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		case 1:
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			if (rom) romMode = true;
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			break;
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	}
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	invalidateDeviceRWCache();
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}
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void MSXMegaRam::setBank(byte page, byte block)
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{
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	bank[page] = block & maskBlocks;
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	uint16_t adr = page * 0x2000;
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	invalidateDeviceRWCache(adr + 0x0000, 0x2000);
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	invalidateDeviceRWCache(adr + 0x8000, 0x2000);
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}
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template<typename Archive>
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void MSXMegaRam::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<MSXDevice>(*this);
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	ar.serialize("ram",       ram,
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	             "bank",      bank,
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	             "writeMode", writeMode,
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	             "romMode",   romMode);
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}
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INSTANTIATE_SERIALIZE_METHODS(MSXMegaRam);
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REGISTER_MSXDEVICE(MSXMegaRam, "MegaRAM");
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} // namespace openmsx