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#include "MegaFlashRomSCCPlusSD.hh"
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#include "CheckedRam.hh"
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#include "SdCard.hh"
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#include "CacheLine.hh"
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#include "DummyAY8910Periphery.hh"
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#include "MSXCPUInterface.hh"
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#include "serialize.hh"
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#include "enumerate.hh"
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#include "narrow.hh"
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#include "ranges.hh"
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#include "xrange.hh"
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#include <array>
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#include <memory>
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/******************************************************************************
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 * DOCUMENTATION AS PROVIDED BY MANUEL PAZOS, WHO DEVELOPED THE CARTRIDGE     *
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 ******************************************************************************
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--------------------------------------------------------------------------------
24 
MegaFlashROM SCC+ SD Technical Details
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(c) Manuel Pazos 24-02-2014
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--------------------------------------------------------------------------------
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[Main features]
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 - 8192 KB flashROM memory
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 - SD interface (MegaSD)
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 - SCC-I (2312P001)
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 - PSG (AY-3-8910/YM2149)
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 - Mappers: ASCII8, ASCII16, Konami, Konami SCC, linear 64K
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 - Slot expander
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--------------------------------------------------------------------------------
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[Memory]
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 - Model Numonyx / Micron M29W640FB / M29W640GB TSOP48
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 - Datasheet: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/parallel/m29w/m29w640f.pdf
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              https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/parallel/m29w/m29w640g.pdf
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 - Block layout:
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     #00000 8K x 8
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     #10000 64K x 127
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 - Command addresses:
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     #4555 and #4AAA
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 - FlashROM ID:
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    ID_M29W640FB    #FD
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    ID_M29W640GB    #7E 10 00
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--------------------------------------------------------------------------------
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[PSG]
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 The PSG included in the cartridge is mapped to ports #10-#12
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 Port #A0 -> #10
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 Port #A1 -> #11
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 Port #A2 -> #12
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 The PSG is read only.
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--------------------------------------------------------------------------------
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[Cartridge layout]
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    - Subslot 0: Recovery - 16K linear (Visible on page 1 and 2)
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    - Subslot 1: MegaFlashROM SCC+ - 7104K (multiple mapper support)
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    - Subslot 2: RAM (when available)
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    - Subslot 3: MegaSD - 1024K (ASC8 mapper)
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--------------------------------------------------------------------------------
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[FlashROM layout]
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#000000+----------------+
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       |    Recovery    | 16K - Subslot 0 (Note: Blocks are write protected
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by VPP/WD pin)
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       +----------------+
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       |   DSK Kernel   | 16K
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       +----------------+
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       |    Not used    | 32K
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#010000+----------------+
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       |                |
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       |                |
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       | MegaFlashROM   | 7104K - Subslot 1
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       |                |
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       |                |
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#700000+----------------+
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       |                |
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       |     MegaSD     | 1024K - Subslot 3
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       |                |
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       +----------------+
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--------------------------------------------------------------------------------
98 
[Subslot register (#FFFF)]
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    Available when writing at #FFFF in the cartridge slot.
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    Reading that address will return all the bits inverted.
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    Default value = 0
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--------------------------------------------------------------------------------
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[Subslot 0: RECOVERY]
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    Size 16K
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    Common ROM (Without mapper).
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    Visible on pages 1 and 2 (mirrored all over the slot)
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--------------------------------------------------------------------------------
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[Subslot 1: MegaFlashROM SCC+ SD]
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  [REGISTERS]
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    [MAPPER REGISTER (#7FFF)]
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    7	mapper mode 1: \ #00 = SCC,  #40 = 64K
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    6	mapper mode 0: / #80 = ASC8, #C0 = ASC16
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    5	mapper mode  :   Select Konami mapper (0=SCC or 1=normal)
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    4
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    3	Disable #4000-#5FFF mapper in Konami mode
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    2	Disable this mapper register #7FFF
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    1	Disable mapper and offset registers
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    0	Enable 512K mapper limit in SCC mapper or 256K limit in Konami mapper
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    [OFFSET REGISTER (#7FFD)]
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    7-0 Offset value bits 7-0
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    [OFFSET REGISTER (#7FFE)]
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    1	Offset bit 9
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    0	Offset bit 8
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    [CONFIG REGISTER (#7FFC)]
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    7	Disable config register (1 = Disabled)
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    6
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    5	Disable SRAM (i.e. the RAM in subslot 2)
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    4	DSK mode (1 = On): Bank 0 and 1 are remapped to DSK kernel (config banks 2-3)
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    3	Cartridge PSG also mapped to ports #A0-#A3
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    2	Subslots disabled (1 = Disabled) Only MegaFlashROM SCC+ is available.
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    1	FlashROM Block protect (1 = Protect) VPP_WD pin
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    0	FlashROM write enable (1 = Enabled)
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  [MAPPERS]
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   - ASCII 8:    Common ASC8 mapper
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   - ASCII 16:   Common ASC16 mapper
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   - Konami:     Common Konami mapper.
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                 Bank0 (#4000-#5FFF) can be also changed unless [MAPPER REGISTER] bit 3 is 1
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   - Konami SCC: Common Konami SCC mapper
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   - Linear 64:  #0000-#3FFF bank0
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                 #4000-#7FFF bank1
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                 #8000-#BFFF bank2
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                 #C000-#FFFF bank3
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                 Banks mapper registers addresses = Konami
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  [DEFAULT VALUES]
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   - MAPPER REGISTER = 0
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   - CONFIG REGISTER = %00000011
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   - MapperBank0 = 0
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   - MapperBank1 = 1
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   - MapperBank2 = 2
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   - MapperBank3 = 3
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   - BankOffset = 0
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   - Subslot register = 0
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  [LOGIC]
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  Bank0   <=    "1111111010" when CONFIG REGISTER(4) = '1' and MapperBank0 = "0000000000" else  ; DSK mode
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                MapperBank0 + bankOffset;
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  Bank1   <=    "1111111011" when CONFIG REGISTER(4) = '1' and MapperBank1 = "0000000001" else  ; DSK mode
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                MapperBank1 + bankOffset;
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  Bank2   <=    MapperBank2 + bankOffset;
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  Bank3   <=    MapperBank3 + bankOffset;
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  RamAdr  <=
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                -- Mapper in 64K mode
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                Bank0(8 downto 0) & adr(13 downto 0) when adr(15 downto 14) = "00" else  --#0000-#3FFF
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                Bank1(8 downto 0) & adr(13 downto 0) when adr(15 downto 14) = "01" else  --#4000-#7FFF
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                Bank2(8 downto 0) & adr(13 downto 0) when adr(15 downto 14) = "10" else  --#8000-#BFFF
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                Bank3(8 downto 0) & adr(13 downto 0) when adr(15 downto 14) = "11" else  --#C000-#FFFF
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                -- Mapper in SCC, ASC8 or ASC16 modes
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                Bank0(9 downto 0) & adr(12 downto 0) when adr(14 downto 13) = "10" else  --#4000-#5FFF
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                Bank1(9 downto 0) & adr(12 downto 0) when adr(14 downto 13) = "11" else  --#6000-#7FFF
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                Bank2(9 downto 0) & adr(12 downto 0) when adr(14 downto 13) = "00" else  --#8000-#9FFF
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                Bank3(9 downto 0) & adr(12 downto 0);                                    --#A000-#BFFF
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  Note: It is possible to access the whole flashROM from the MegaFlashROM SCC+
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  SD using the offsets register!
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--------------------------------------------------------------------------------
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[Subslot 2: 512K RAM expansion]
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  Mapper ports:
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    Page 0 = #FC
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    Page 1 = #FD
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    Page 2 = #FE
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    Page 3 = #FF
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  Default bank values:
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    Page 0 = 3
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    Page 1 = 2
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    Page 2 = 1
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    Page 3 = 0
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  Disabled when [CONFIG REGISTER] bit 5 = 1
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  Since mapper ports must not be read, as stated on MSX Technical Handbook, and
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  mapper ports as read only, as stated on MSX Datapack, all read operations on
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  these ports will not return any value.
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UPDATE:
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  Initial version indeed did not support reading the memory mapper ports. But
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  upon user request this feature was added later.
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--------------------------------------------------------------------------------
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[Subslot 3: MegaSD]
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  Mapper type: ASCII8
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  Default mapper values:
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    Bank0 = 0
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    Bank1 = 1
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    Bank2 = 0
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    Bank3 = 0
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  Memory range 1024K: Banks #00-#7F are mirrored in #80-#FF (except registers
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  bank #40-#7F)
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  Memory registers area (Bank #40-#7F):
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    #4000-#57FF: SD card access (R/W)
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                 #4000-#4FFF: /CS signal = 0 - SD enabled
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                 #5000-#5FFF: /CS signal = 1 - SD disabled
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    #5800-#5FFF: SD slot select (bit 0: 0 = SD slot 1, 1 = SD slot 2)
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  Writes to these registers do not write through to the FlashROM.
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  Cards work in SPI mode.
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  Signals used: CS, DI, DO, SCLK
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  When reading, 8 bits are read from DO
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  When writing, 8 bits are written to DI
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  SD specifications: https://www.sdcard.org/downloads/pls/simplified_specs/part1_410.pdf
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******************************************************************************/
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static constexpr unsigned MEMORY_MAPPER_SIZE = 512;
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static constexpr uint8_t MEMORY_MAPPER_MASK = (MEMORY_MAPPER_SIZE / 16) - 1;
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namespace openmsx {
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MegaFlashRomSCCPlusSD::MegaFlashRomSCCPlusSD(DeviceConfig& config)
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	: MSXDevice(config)
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	, flash("MFR SCC+ SD flash", AmdFlashChip::M29W640GB, {}, config)
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	, scc("MFR SCC+ SD SCC-I", config, getCurrentTime(), SCC::Mode::Compatible)
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	, psg("MFR SCC+ SD PSG", DummyAY8910Periphery::instance(), config,
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	      getCurrentTime())
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	, checkedRam(config.getChildDataAsBool("hasmemorymapper", true) ?
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		std::make_unique<CheckedRam>(config, getName() + " memory mapper", "memory mapper", MEMORY_MAPPER_SIZE * 1024)
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		: nullptr)
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	, mapperIO(checkedRam ? std::make_unique<MapperIO>(*this) : nullptr) // handles ports 0xfc-0xff
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{
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	// adjust PSG volume, see details in https://github.com/openMSX/openMSX/issues/1934
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	// note: this is a theoretical value. The actual relative volume should be measured!
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	psg.setSoftwareVolume(21000.0f/9000.0f, getCurrentTime());
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	powerUp(getCurrentTime());
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	getCPUInterface().register_IO_Out_range(0x10, 2, this);
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	sdCard[0] = std::make_unique<SdCard>(DeviceConfig(config, config.findChild("sdcard1")));
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	sdCard[1] = std::make_unique<SdCard>(DeviceConfig(config, config.findChild("sdcard2")));
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}
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MegaFlashRomSCCPlusSD::~MegaFlashRomSCCPlusSD()
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{
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	// unregister extra PSG I/O ports
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	updateConfigReg(3);
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	getCPUInterface().unregister_IO_Out_range(0x10, 2, this);
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}
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void MegaFlashRomSCCPlusSD::powerUp(EmuTime time)
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{
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	scc.powerUp(time);
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	reset(time);
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}
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void MegaFlashRomSCCPlusSD::reset(EmuTime time)
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{
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	mapperReg = 0;
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	offsetReg = 0;
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	updateConfigReg(3);
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	subslotReg = 0;
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	ranges::iota(bankRegsSubSlot1, uint16_t(0));
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	sccMode = 0;
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	ranges::iota(sccBanks, byte(0));
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	scc.reset(time);
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	psgLatch = 0;
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	psg.reset(time);
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	flash.reset();
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	// memory mapper
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	for (auto [i, mr] : enumerate(memMapperRegs)) {
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		mr = byte(3 - i);
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	}
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	for (auto [bank, reg] : enumerate(bankRegsSubSlot3)) {
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		reg = (bank == 1) ? 1 : 0;
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	}
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	selectedCard = 0;
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	invalidateDeviceRWCache(); // flush all to be sure
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}
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byte MegaFlashRomSCCPlusSD::getSubSlot(unsigned addr) const
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{
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	return isSlotExpanderEnabled() ?
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		(subslotReg >> (2 * (addr >> 14))) & 3 : 1;
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}
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void MegaFlashRomSCCPlusSD::writeToFlash(unsigned addr, byte value, EmuTime time)
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{
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	if (isFlashRomWriteEnabled()) {
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		flash.write(addr, value, time);
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	} else {
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		// flash is write protected, this is implemented by not passing
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		// writes to flash at all.
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	}
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}
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byte MegaFlashRomSCCPlusSD::peekMem(uint16_t addr, EmuTime time) const
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{
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	if (isSlotExpanderEnabled() && (addr == 0xFFFF)) {
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		// read subslot register
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		return subslotReg ^ 0xFF;
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	}
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	switch (getSubSlot(addr)) {
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		case 0: return peekMemSubSlot0(addr, time);
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		case 1: return peekMemSubSlot1(addr, time);
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		case 2: return isMemoryMapperEnabled() ?
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				peekMemSubSlot2(addr) : 0xFF;
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		case 3: return peekMemSubSlot3(addr, time);
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		default: UNREACHABLE;
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	}
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}
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byte MegaFlashRomSCCPlusSD::readMem(uint16_t addr, EmuTime time)
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{
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	if (isSlotExpanderEnabled() && (addr == 0xFFFF)) {
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		// read subslot register
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		return subslotReg ^ 0xFF;
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	}
377
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	switch (getSubSlot(addr)) {
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		case 0: return readMemSubSlot0(addr, time);
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		case 1: return readMemSubSlot1(addr, time);
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		case 2: return isMemoryMapperEnabled() ?
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				readMemSubSlot2(addr) : 0xFF;
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		case 3: return readMemSubSlot3(addr, time);
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		default: UNREACHABLE;
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	}
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}
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const byte* MegaFlashRomSCCPlusSD::getReadCacheLine(uint16_t addr) const
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{
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	if (isSlotExpanderEnabled() &&
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		((addr & CacheLine::HIGH) == (0xFFFF & CacheLine::HIGH))) {
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		// read subslot register
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		return nullptr;
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	}
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	switch (getSubSlot(addr)) {
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		case 0: return getReadCacheLineSubSlot0(addr);
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		case 1: return getReadCacheLineSubSlot1(addr);
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		case 2: return isMemoryMapperEnabled() ?
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				getReadCacheLineSubSlot2(addr) : unmappedRead.data();
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		case 3: return getReadCacheLineSubSlot3(addr);
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		default: UNREACHABLE;
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	}
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}
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void MegaFlashRomSCCPlusSD::writeMem(uint16_t addr, byte value, EmuTime time)
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{
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	if (isSlotExpanderEnabled() && (addr == 0xFFFF)) {
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		// write subslot register
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		byte diff = value ^ subslotReg;
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		subslotReg = value;
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		for (auto i : xrange(4)) {
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			if (diff & (3 << (2 * i))) {
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				invalidateDeviceRWCache(0x4000 * i, 0x4000);
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			}
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		}
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	}
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	switch (getSubSlot(addr)) {
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		case 0: writeMemSubSlot0(addr, value, time); break;
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		case 1: writeMemSubSlot1(addr, value, time); break;
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		case 2: if (isMemoryMapperEnabled()) {
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				writeMemSubSlot2(addr, value);
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			}
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			break;
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		case 3: writeMemSubSlot3(addr, value, time); break;
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		default: UNREACHABLE;
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	}
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}
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byte* MegaFlashRomSCCPlusSD::getWriteCacheLine(uint16_t addr)
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{
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	if (isSlotExpanderEnabled() &&
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		((addr & CacheLine::HIGH) == (0xFFFF & CacheLine::HIGH))) {
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		// read subslot register
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		return nullptr;
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	}
438
439 
	switch (getSubSlot(addr)) {
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		case 0: return getWriteCacheLineSubSlot0(addr);
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		case 1: return getWriteCacheLineSubSlot1(addr);
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		case 2: return isMemoryMapperEnabled() ?
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				getWriteCacheLineSubSlot2(addr) : unmappedWrite.data();
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		case 3: return getWriteCacheLineSubSlot3(addr);
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		default: UNREACHABLE;
446 
	}
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}
448
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/////////////////////// sub slot 0 ////////////////////////////////////////////
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byte MegaFlashRomSCCPlusSD::readMemSubSlot0(uint16_t addr, EmuTime time)
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{
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	// read from the first 16kB of flash
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	// Pazos: ROM and flash can be accessed in all pages (0,1,2,3) (#0000-#FFFF)
455 
	return flash.read(addr & 0x3FFF, time);
456 
}
457
458 
byte MegaFlashRomSCCPlusSD::peekMemSubSlot0(uint16_t addr, EmuTime time) const
459 
{
460 
	// read from the first 16kB of flash
461 
	// Pazos: ROM and flash can be accessed in all pages (0,1,2,3) (#0000-#FFFF)
462 
	return flash.peek(addr & 0x3FFF, time);
463 
}
464
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const byte* MegaFlashRomSCCPlusSD::getReadCacheLineSubSlot0(uint16_t addr) const
466 
{
467 
	return flash.getReadCacheLine(addr & 0x3FFF);
468 
}
469
470 
void MegaFlashRomSCCPlusSD::writeMemSubSlot0(uint16_t addr, byte value, EmuTime time)
471 
{
472 
	// Pazos: ROM and flash can be accessed in all pages (0,1,2,3) (#0000-#FFFF)
473 
	writeToFlash(addr & 0x3FFF, value, time);
474 
}
475
476 
byte* MegaFlashRomSCCPlusSD::getWriteCacheLineSubSlot0(uint16_t /*addr*/)
477 
{
478 
	return nullptr; // flash isn't cacheable
479 
}
480
481 
/////////////////////// sub slot 1 ////////////////////////////////////////////
482
483 
void MegaFlashRomSCCPlusSD::updateConfigReg(byte value)
484 
{
485 
	if ((value ^ configReg) & 0x08) {
486 
		if (value & 0x08) {
487 
			for (auto port : {0xa0, 0xa1}) {
488 
				getCPUInterface().register_IO_Out(narrow_cast<byte>(port), this);
489 
			}
490 
		} else {
491 
			for (auto port : {0xa0, 0xa1}) {
492 
				getCPUInterface().unregister_IO_Out(narrow_cast<byte>(port), this);
493 
			}
494 
		}
495 
	}
496 
	configReg = value;
497 
	flash.setVppWpPinLow(isFlashRomBlockProtectEnabled());
498 
	invalidateDeviceRWCache(); // flush all to be sure
499 
}
500
501 
MegaFlashRomSCCPlusSD::SCCEnable MegaFlashRomSCCPlusSD::getSCCEnable() const
502 
{
503 
	if ((sccMode & 0x20) && (sccBanks[3] & 0x80)) {
504 
		return EN_SCCPLUS;
505 
	} else if ((!(sccMode & 0x20)) && ((sccBanks[2] & 0x3F) == 0x3F)) {
506 
		return EN_SCC;
507 
	} else {
508 
		return EN_NONE;
509 
	}
510 
}
511
512 
unsigned MegaFlashRomSCCPlusSD::getFlashAddrSubSlot1(unsigned addr) const
513 
{
514 
	unsigned page = is64KmapperConfigured() ? (addr >> 14) : ((addr >> 13) - 2);
515 
	unsigned size = is64KmapperConfigured() ? 0x4000 : 0x2000;
516
517 
	if (page >= 4) return unsigned(-1); // outside [0x4000, 0xBFFF] for non-64K mapper
518
519 
	unsigned bank = bankRegsSubSlot1[page];
520 
	if        (isDSKmodeEnabled() && (page == 0) && (bank == 0)) {
521 
		bank = 0x3FA;
522 
	} else if (isDSKmodeEnabled() && (page == 1) && (bank == 1)) {
523 
		bank = 0x3FB;
524 
	} else { // not DSK mode
525 
		bank += offsetReg;
526 
	}
527
528 
	unsigned tmp = (bank * size) + (addr & (size - 1));
529 
	return (tmp +  0x010000) & 0x7FFFFF; // wrap at 8MB
530 
}
531
532 
byte MegaFlashRomSCCPlusSD::readMemSubSlot1(uint16_t addr, EmuTime time)
533 
{
534 
	if (isKonamiSCCmapperConfigured()) { // Konami SCC
535 
		SCCEnable enable = getSCCEnable();
536 
		if (((enable == EN_SCC)     && (0x9800 <= addr) && (addr < 0xA000)) ||
537 
		    ((enable == EN_SCCPLUS) && (0xB800 <= addr) && (addr < 0xC000))) {
538 
			byte val = scc.readMem(narrow_cast<uint8_t>(addr & 0xFF), time);
539 
			return val;
540 
		}
541 
	}
542
543 
	unsigned flashAddr = getFlashAddrSubSlot1(addr);
544 
	return (flashAddr != unsigned(-1))
545 
		? flash.read(flashAddr, time)
546 
		: 0xFF; // unmapped read
547 
}
548
549 
byte MegaFlashRomSCCPlusSD::peekMemSubSlot1(uint16_t addr, EmuTime time) const
550 
{
551 
	if (isKonamiSCCmapperConfigured()) { // Konami SCC
552 
		SCCEnable enable = getSCCEnable();
553 
		if (((enable == EN_SCC)     && (0x9800 <= addr) && (addr < 0xA000)) ||
554 
		    ((enable == EN_SCCPLUS) && (0xB800 <= addr) && (addr < 0xC000))) {
555 
			byte val = scc.peekMem(narrow_cast<uint8_t>(addr & 0xFF), time);
556 
			return val;
557 
		}
558 
	}
559
560 
	unsigned flashAddr = getFlashAddrSubSlot1(addr);
561 
	return (flashAddr != unsigned(-1))
562 
		? flash.peek(flashAddr, time)
563 
		: 0xFF; // unmapped read
564 
}
565
566 
const byte* MegaFlashRomSCCPlusSD::getReadCacheLineSubSlot1(uint16_t addr) const
567 
{
568 
	if (isKonamiSCCmapperConfigured()) {
569 
		SCCEnable enable = getSCCEnable();
570 
		if (((enable == EN_SCC)     && (0x9800 <= addr) && (addr < 0xA000)) ||
571 
		    ((enable == EN_SCCPLUS) && (0xB800 <= addr) && (addr < 0xC000))) {
572 
			return nullptr;
573 
		}
574 
	}
575
576 
	unsigned flashAddr = getFlashAddrSubSlot1(addr);
577 
	return (flashAddr != unsigned(-1))
578 
		? flash.getReadCacheLine(flashAddr)
579 
		: unmappedRead.data();
580 
}
581
582 
void MegaFlashRomSCCPlusSD::writeMemSubSlot1(uint16_t addr, byte value, EmuTime time)
583 
{
584 
	// address is calculated before writes to other regions take effect
585 
	unsigned flashAddr = getFlashAddrSubSlot1(addr);
586
587 
	// There are several overlapping functional regions in the address
588 
	// space. A single write can trigger behaviour in multiple regions. In
589 
	// other words there's no priority amongst the regions where a higher
590 
	// priority region blocks the write from the lower priority regions.
591 
	// This only goes for places where the flash is 'seen', so not for the
592 
	// SCC registers and the SSR
593
594 
	if (!isConfigRegDisabled() && (addr == 0x7FFC)) {
595 
		// write config register
596 
		updateConfigReg(value);
597 
	}
598
599 
	if (!isMapperRegisterDisabled() && (addr == 0x7FFF)) {
600 
		// write mapper register
601 
		mapperReg = value;
602 
		invalidateDeviceRWCache(); // flush all to be sure
603 
	}
604
605 
	if (!areBankRegsAndOffsetRegsDisabled() && (addr == 0x7FFD)) {
606 
		// write offset register low part
607 
		offsetReg = (offsetReg & 0x300) | value;
608 
		invalidateDeviceRWCache();
609 
	}
610
611 
	if (!areBankRegsAndOffsetRegsDisabled() && (addr == 0x7FFE)) {
612 
		// write offset register high part (bit 8 and 9)
613 
		offsetReg = (offsetReg & 0xFF) + ((value & 0x3) << 8);
614 
		invalidateDeviceRWCache();
615 
	}
616
617 
	if (isKonamiSCCmapperConfigured()) {
618 
		// Konami-SCC
619 
		if ((addr & 0xFFFE) == 0xBFFE) {
620 
			sccMode = value;
621 
			scc.setMode((value & 0x20) ? SCC::Mode::Plus
622 
			                           : SCC::Mode::Compatible);
623 
			invalidateDeviceRWCache(0x9800, 0x800);
624 
			invalidateDeviceRWCache(0xB800, 0x800);
625 
		}
626 
		SCCEnable enable = getSCCEnable();
627 
		bool isRamSegment2 = ((sccMode & 0x24) == 0x24) ||
628 
		                     ((sccMode & 0x10) == 0x10);
629 
		bool isRamSegment3 = ((sccMode & 0x10) == 0x10);
630 
		if (((enable == EN_SCC)     && !isRamSegment2 &&
631 
		     (0x9800 <= addr) && (addr < 0xA000)) ||
632 
		    ((enable == EN_SCCPLUS) && !isRamSegment3 &&
633 
		     (0xB800 <= addr) && (addr < 0xC000))) {
634 
			scc.writeMem(narrow_cast<uint8_t>(addr & 0xFF), value, time);
635 
			return; // Pazos: when SCC registers are selected flashROM is not seen, so it does not accept commands.
636 
		}
637 
	}
638
639 
	unsigned page8kB = (addr >> 13) - 2;
640 
	if (!areBankRegsAndOffsetRegsDisabled() && (page8kB < 4)) {
641 
		// (possibly) write to bank registers
642 
		switch (mapperReg & 0xE0) {
643 
		case 0x00:
644 
			// Konami-SCC
645 
			if ((addr & 0x1800) == 0x1000) {
646 
				// Storing 'sccBanks' may seem redundant at
647 
				// first, but it's required to calculate
648 
				// whether the SCC is enabled or not.
649 
				sccBanks[page8kB] = value;
650 
				// Masking of the mapper bits is done on
651 
				// write (and only in Konami(-scc) mode)
652 
				byte mask = areKonamiMapperLimitsEnabled() ? 0x3F : 0xFF;
653 
				bankRegsSubSlot1[page8kB] = value & mask;
654 
				invalidateDeviceRWCache(0x4000 + 0x2000 * page8kB, 0x2000);
655 
			}
656 
			break;
657 
		case 0x20: {
658 
			// Konami
659 
			if (isWritingKonamiBankRegisterDisabled() && (addr < 0x6000)) {
660 
				// Switching 0x4000-0x5FFF disabled.
661 
				// This bit blocks writing to the bank register
662 
				// (an alternative was forcing a 0 on read).
663 
				// It only has effect in Konami mode.
664 
				break;
665 
			}
666 
			// Making of the mapper bits is done on
667 
			// write (and only in Konami(-scc) mode)
668 
			if ((addr < 0x5000) || ((0x5800 <= addr) && (addr < 0x6000))) break; // only SCC range works
669 
			byte mask = areKonamiMapperLimitsEnabled() ? 0x1F : 0xFF;
670 
			bankRegsSubSlot1[page8kB] = value & mask;
671 
			invalidateDeviceRWCache(0x4000 + 0x2000 * page8kB, 0x2000);
672 
			break;
673 
		}
674 
		case 0x40:
675 
		case 0x60:
676 
			// 64kB
677 
			bankRegsSubSlot1[page8kB] = value;
678 
			invalidateDeviceRWCache(0x0000 + 0x4000 * page8kB, 0x4000);
679 
			break;
680 
		case 0x80:
681 
		case 0xA0:
682 
			// ASCII-8
683 
			if ((0x6000 <= addr) && (addr < 0x8000)) {
684 
				byte bank = (addr >> 11) & 0x03;
685 
				bankRegsSubSlot1[bank] = value;
686 
				invalidateDeviceRWCache(0x4000 + 0x2000 * bank, 0x2000);
687 
			}
688 
			break;
689 
		case 0xC0:
690 
		case 0xE0:
691 
			// ASCII-16
692 
			// This behaviour is confirmed by Manuel Pazos (creator
693 
			// of the cartridge): ASCII-16 uses all 4 bank registers
694 
			// and one bank switch changes 2 registers at once.
695 
			// This matters when switching mapper mode, because
696 
			// the content of the bank registers is unchanged after
697 
			// a switch.
698 
			// In the first versions of the VHDL code, the bankRegs
699 
			// were 8-bit, but due to the construction explained
700 
			// above, this results in a maximum size of 2MB for the
701 
			// ASCII-16 mapper, as we throw away 1 bit. Later,
702 
			// Manuel Pazos made an update to use 9 bits for the
703 
			// registers to overcome this limitation. We emulate
704 
			// the updated version now.
705 
			const uint16_t mask = (1 << 9) - 1;
706 
			if ((0x6000 <= addr) && (addr < 0x6800)) {
707 
				bankRegsSubSlot1[0] = (2 * value + 0) & mask;
708 
				bankRegsSubSlot1[1] = (2 * value + 1) & mask;
709 
				invalidateDeviceRWCache(0x4000, 0x4000);
710 
			}
711 
			if ((0x7000 <= addr) && (addr < 0x7800)) {
712 
				bankRegsSubSlot1[2] = (2 * value + 0) & mask;
713 
				bankRegsSubSlot1[3] = (2 * value + 1) & mask;
714 
				invalidateDeviceRWCache(0x8000, 0x4000);
715 
			}
716 
			break;
717 
		}
718 
	}
719
720 
	if (flashAddr != unsigned(-1)) {
721 
		writeToFlash(flashAddr, value, time);
722 
	}
723 
}
724
725 
byte* MegaFlashRomSCCPlusSD::getWriteCacheLineSubSlot1(uint16_t /*addr*/)
726 
{
727 
	return nullptr; // flash isn't cacheable
728 
}
729
730 
/////////////////////// sub slot 2 ////////////////////////////////////////////
731
732 
unsigned MegaFlashRomSCCPlusSD::calcMemMapperAddress(uint16_t address) const
733 
{
734 
	auto bank = memMapperRegs[address >> 14];
735 
	return ((bank & MEMORY_MAPPER_MASK) << 14) | (address & 0x3FFF);
736 
}
737
738 
byte MegaFlashRomSCCPlusSD::readMemSubSlot2(uint16_t addr)
739 
{
740 
	// read from the memory mapper
741 
	return checkedRam->read(calcMemMapperAddress(addr));
742 
}
743
744 
byte MegaFlashRomSCCPlusSD::peekMemSubSlot2(uint16_t addr) const
745 
{
746 
	return checkedRam->peek(calcMemMapperAddress(addr));
747 
}
748
749 
const byte* MegaFlashRomSCCPlusSD::getReadCacheLineSubSlot2(uint16_t addr) const
750 
{
751 
	return checkedRam->getReadCacheLine(calcMemMapperAddress(addr));
752 
}
753
754 
void MegaFlashRomSCCPlusSD::writeMemSubSlot2(uint16_t addr, byte value)
755 
{
756 
	// write to the memory mapper
757 
	checkedRam->write(calcMemMapperAddress(addr), value);
758 
}
759
760 
byte* MegaFlashRomSCCPlusSD::getWriteCacheLineSubSlot2(uint16_t addr)
761 
{
762 
	return checkedRam->getWriteCacheLine(calcMemMapperAddress(addr));
763 
}
764
765 
byte MegaFlashRomSCCPlusSD::MapperIO::readIO(uint16_t port, EmuTime time)
766 
{
767 
	return peekIO(port, time);
768 
}
769
770 
byte MegaFlashRomSCCPlusSD::MapperIO::peekIO(uint16_t port, EmuTime /*time*/) const
771 
{
772 
	return getSelectedSegment(port & 3) | byte(~MEMORY_MAPPER_MASK);
773 
}
774
775 
void MegaFlashRomSCCPlusSD::MapperIO::writeIO(uint16_t port, byte value, EmuTime /*time*/)
776 
{
777 
	mega.memMapperRegs[port & 3] = value & MEMORY_MAPPER_MASK;
778 
	mega.invalidateDeviceRWCache(0x4000 * (port & 0x03), 0x4000);
779 
}
780
781 
byte MegaFlashRomSCCPlusSD::MapperIO::getSelectedSegment(byte page) const
782 
{
783 
	return mega.memMapperRegs[page];
784 
}
785
786 
/////////////////////// sub slot 3 ////////////////////////////////////////////
787
788 
unsigned MegaFlashRomSCCPlusSD::getFlashAddrSubSlot3(unsigned addr) const
789 
{
790 
	unsigned page8kB = (addr >> 13) - 2;
791 
	return (bankRegsSubSlot3[page8kB] & 0x7f) * 0x2000 + (addr & 0x1fff) + 0x700000;
792 
}
793
794 
byte MegaFlashRomSCCPlusSD::readMemSubSlot3(uint16_t addr, EmuTime time)
795 
{
796 
	if (((bankRegsSubSlot3[0] & 0xC0) == 0x40) && ((0x4000 <= addr) && (addr < 0x6000))) {
797 
		// transfer from SD card
798 
		return sdCard[selectedCard]->transfer(0xFF, (addr & 0x1000) != 0);
799 
	}
800
801 
	if ((0x4000 <= addr) && (addr < 0xC000)) {
802 
		// read (flash)rom content
803 
		unsigned flashAddr = getFlashAddrSubSlot3(addr);
804 
		return flash.read(flashAddr, time);
805 
	} else {
806 
		// unmapped read
807 
		return 0xFF;
808 
	}
809 
}
810
811 
byte MegaFlashRomSCCPlusSD::peekMemSubSlot3(uint16_t addr, EmuTime time) const
812 
{
813 
	if ((0x4000 <= addr) && (addr < 0xC000)) {
814 
		// read (flash)rom content
815 
		unsigned flashAddr = getFlashAddrSubSlot3(addr);
816 
		return flash.peek(flashAddr, time);
817 
	} else {
818 
		// unmapped read
819 
		return 0xFF;
820 
	}
821 
}
822
823 
const byte* MegaFlashRomSCCPlusSD::getReadCacheLineSubSlot3(uint16_t addr) const
824 
{
825 
	if (((bankRegsSubSlot3[0] & 0xC0) == 0x40) && ((0x4000 <= addr) && (addr < 0x6000))) {
826 
		return nullptr;
827 
	}
828
829 
	if ((0x4000 <= addr) && (addr < 0xC000)) {
830 
		// (flash)rom content
831 
		unsigned flashAddr = getFlashAddrSubSlot3(addr);
832 
		return flash.getReadCacheLine(flashAddr);
833 
	} else {
834 
		return unmappedRead.data();
835 
	}
836 
}
837
838 
void MegaFlashRomSCCPlusSD::writeMemSubSlot3(uint16_t addr, byte value, EmuTime time)
839 
{
840
841 
	if (((bankRegsSubSlot3[0] & 0xC0) == 0x40) && ((0x4000 <= addr) && (addr < 0x6000))) {
842 
		if (addr >= 0x5800) {
843 
			selectedCard = value & 1;
844 
		} else {
845 
			// transfer to SD card
846 
			sdCard[selectedCard]->transfer(value, (addr & 0x1000) != 0); // ignore return value
847 
		}
848 
	} else {
849 
		// write to flash (first, before modifying bank regs)
850 
		if ((0x4000 <= addr) && (addr < 0xC000)) {
851 
			unsigned flashAddr = getFlashAddrSubSlot3(addr);
852 
			writeToFlash(flashAddr, value, time);
853 
		}
854
855 
		// ASCII-8 mapper
856 
		if ((0x6000 <= addr) && (addr < 0x8000)) {
857 
			byte page8kB = (addr >> 11) & 0x03;
858 
			bankRegsSubSlot3[page8kB] = value;
859 
			invalidateDeviceRWCache(0x4000 + 0x2000 * page8kB, 0x2000);
860 
		}
861 
	}
862 
}
863
864 
byte* MegaFlashRomSCCPlusSD::getWriteCacheLineSubSlot3(uint16_t /*addr*/)
865 
{
866 
	return nullptr; // flash isn't cacheable
867 
}
868
869 
/////////////////////// I/O ////////////////////////////////////////////
870
871 
void MegaFlashRomSCCPlusSD::writeIO(uint16_t port, byte value, EmuTime time)
872 
{
873 
	switch (port & 0xFF) {
874 
		case 0xA0:
875 
			if (!isPSGalsoMappedToNormalPorts()) return;
876 
			[[fallthrough]];
877 
		case 0x10:
878 
			psgLatch = value & 0x0F;
879 
			break;
880
881 
		case 0xA1:
882 
			if (!isPSGalsoMappedToNormalPorts()) return;
883 
			[[fallthrough]];
884 
		case 0x11:
885 
			psg.writeRegister(psgLatch, value, time);
886 
			break;
887
888 
		default:
889 
			UNREACHABLE;
890 
	}
891 
}
892
893 
template<typename Archive>
894 
void MegaFlashRomSCCPlusSD::serialize(Archive& ar, unsigned /*version*/)
895 
{
896 
	// skip MSXRom base class
897 
	ar.template serializeBase<MSXDevice>(*this);
898
899 
	// overall
900 
	ar.serialize("flash",      flash,
901 
	             "subslotReg", subslotReg);
902
903 
	// subslot 0 stuff
904 
	// (nothing)
905
906 
	// subslot 1 stuff
907 
	ar.serialize("scc",       scc,
908 
	             "sccMode",   sccMode,
909 
	             "sccBanks",  sccBanks,
910 
	             "psg",       psg,
911 
	             "psgLatch",  psgLatch,
912 
	             "configReg", configReg,
913 
	             "mapperReg", mapperReg,
914 
	             "offsetReg", offsetReg,
915 
	             "bankRegsSubSlot1", bankRegsSubSlot1);
916 
	if constexpr (Archive::IS_LOADER) {
917 
		// Re-register PSG ports (if needed)
918 
		byte tmp = configReg;
919 
		configReg = 3; // set to un-registered
920 
		updateConfigReg(tmp); // restore correct value
921 
	}
922
923 
	// subslot 2 stuff
924 
	// TODO ar.serialize("checkedRam", checkedRam);
925 
	if (checkedRam) ar.serialize("ram", checkedRam->getUncheckedRam());
926 
	ar.serialize("memMapperRegs", memMapperRegs);
927
928 
	// subslot 3 stuff
929 
	ar.serialize("bankRegsSubSlot3", bankRegsSubSlot3,
930 
	             "selectedCard",     selectedCard,
931 
	             "sdCard0",          *sdCard[0],
932 
	             "sdCard1",          *sdCard[1]);
933 
}
934 
INSTANTIATE_SERIALIZE_METHODS(MegaFlashRomSCCPlusSD);
935 
REGISTER_MSXDEVICE(MegaFlashRomSCCPlusSD, "MegaFlashRomSCCPlusSD");
936
937 
} // namespace openmsx