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◆ main openmsx / src / memory / RomRamFile.cc
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/**
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 * Tecall MSX RAMFile TM220
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 *
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 * This is a cartridge with 16kB ROM and 16kB RAM (powered by a battery). It
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 * offers BASIC commands to load/save files to this RAM. See manual for more
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 * details:
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 *     http://www.msxarchive.nl/pub/msx/graphics/jpg/hardware/manuals/
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 *
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 * The ROM is visible in region 0x4000-0x8000.
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 * The RAM is visible in region 0x8000-0xC000.
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 * Reading ROM/RAM works as expected, but writing to RAM is special.
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 *
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 * The /WE signal of the RAM chip (actually implemented as 2x8kB RAM chips) is
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 * calculated from the /WE signal on the MSX cartridge slot plus 3 output bits
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 * from a 74LS164 shift-register. The input of this shift-register is 'D2 & D6'
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 * of the cartridge slot. The clock input of the shift-register is a
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 * combination of the /CS1 and /M1 cartridge signals. This means that on each
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 * (first byte of an) instruction fetch from the ROM, 2 bits of the fetched
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 * opcode are combined and shifted in an 8-bit value. 3 of those shifted bits
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 * need to have a specific value to allow write. See implementation below for
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 * more details.
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 *
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 * So in summary, the TM220 monitors which instructions are fetched from ROM
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 * and only allows to write to RAM after certain sequences of instructions.
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 */
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#include "RomRamFile.hh"
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#include "MSXCPU.hh"
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#include "narrow.hh"
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#include "serialize.hh"
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#include <memory>
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namespace openmsx {
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RomRamFile::RomRamFile(const DeviceConfig& config, Rom&& rom_)
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	: MSXRom(config, std::move(rom_))
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	, cpu(getCPU())
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{
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	sram = std::make_unique<SRAM>(getName() + " SRAM", 0x4000, config);
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	reset(EmuTime::dummy());
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}
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void RomRamFile::reset(EmuTime /*time*/)
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{
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	shiftValue = 0;
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}
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byte RomRamFile::readMem(uint16_t address, EmuTime /*time*/)
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{
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	if ((0x4000 <= address) && (address < 0x8000)) {
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		byte result = rom[address & 0x1fff];
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		if (cpu.isM1Cycle(address)) {
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			bool tmp = (result & 0x44) == 0x44;
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			shiftValue = narrow_cast<byte>((shiftValue << 1) | byte(tmp));
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		}
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		return result;
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	} else if ((0x8000 <= address) && (address < 0xC000)) {
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		return (*sram)[address & 0x3fff];
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	} else {
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		return 0xff;
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	}
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}
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byte RomRamFile::peekMem(uint16_t address, EmuTime /*time*/) const
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{
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	if ((0x4000 <= address) && (address < 0x8000)) {
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		return rom[address & 0x1fff];
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	} else if ((0x8000 <= address) && (address < 0xC000)) {
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		return (*sram)[address & 0x3fff];
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	} else {
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		return 0xff;
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	}
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}
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const byte* RomRamFile::getReadCacheLine(uint16_t address) const
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{
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	if ((0x4000 <= address) && (address < 0x8000)) {
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		// reads from ROM are not cacheable because of the M1 stuff
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		return nullptr;
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	} else if ((0x8000 <= address) && (address < 0xC000)) {
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		return &(*sram)[address & 0x3fff];
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	} else {
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		return unmappedRead.data();
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	}
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}
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void RomRamFile::writeMem(uint16_t address, byte value, EmuTime /*time*/)
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{
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	if ((0x8000 <= address) && (address < 0xC000) &&
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	    ((shiftValue & 0x31) == 0x11)) {
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		sram->write(address & 0x3fff, value);
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	}
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}
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byte* RomRamFile::getWriteCacheLine(uint16_t address)
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{
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	if ((0x8000 <= address) && (address < 0xC000)) {
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		// writes to SRAM are not cacheable because of sync-to-disk
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		return nullptr;
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	} else {
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		return unmappedWrite.data();
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	}
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}
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template<typename Archive>
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void RomRamFile::serialize(Archive& ar, unsigned /*version*/)
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{
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	// skip MSXRom base class
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	ar.template serializeBase<MSXDevice>(*this);
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	ar.serialize("shiftValue", shiftValue);
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}
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INSTANTIATE_SERIALIZE_METHODS(RomRamFile);
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REGISTER_MSXDEVICE(RomRamFile, "RomRamFile");
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} // namespace openmsx