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◆ main openmsx / src / memory / RomHalnote.cc
4.5 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
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/*
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 * HALNOTE mapper
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 *
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 * This info is extracted from the romMapperHalnote.c source in blueMSX,
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 * implemented by white_cat.
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 *
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 * This is a 1024kB mapper, it's divided in 128 pages of 8kB. The last 512kB
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 * can also be mapped as 256 pages of 2kB. There is 16kB SRAM.
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 *
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 * Main bank-switch registers:
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 *   bank 0,  region: [0x4000-0x5FFF],  switch addr: 0x4FFF
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 *   bank 1,  region: [0x6000-0x7FFF],  switch addr: 0x6FFF
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 *   bank 2,  region: [0x8000-0x9FFF],  switch addr: 0x8FFF
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 *   bank 3,  region: [0xA000-0xBFFF],  switch addr: 0xAFFF
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 * Sub-bank-switch registers:
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 *   bank 0,  region: [0x7000-0x77FF],  switch addr: 0x77FF
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 *   bank 1,  region: [0x7800-0x7FFF],  switch addr: 0x7FFF
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 * Note that the two sub-banks overlap with main bank 1!
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 *
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 * The upper bit (0x80) of the first two main bank-switch registers are special:
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 *   bank 0, bit7   SRAM      enabled in [0x0000-0x3FFF]  (1=enabled)
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 *   bank 1, bit7   submapper enabled in [0x7000-0x7FFF]  (1=enabled)
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 * If enabled, the submapper shadows (part of) main bank 1.
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 */
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#include "RomHalnote.hh"
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#include "SRAM.hh"
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#include "CacheLine.hh"
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#include "MSXException.hh"
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#include "serialize.hh"
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#include "one_of.hh"
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#include "xrange.hh"
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#include <memory>
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namespace openmsx {
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RomHalnote::RomHalnote(const DeviceConfig& config, Rom&& rom_)
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	: Rom8kBBlocks(config, std::move(rom_))
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{
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	if (rom.size() != 0x100000) {
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		throw MSXException(
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			"Rom for HALNOTE mapper must be exactly 1MB in size.");
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	}
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	sram = std::make_unique<SRAM>(getName() + " SRAM", 0x4000, config);
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	reset(EmuTime::dummy());
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}
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void RomHalnote::reset(EmuTime /*time*/)
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{
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	subBanks[0] = subBanks[1] = 0;
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	sramEnabled = false;
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	subMapperEnabled = false;
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	setUnmapped(0);
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	setUnmapped(1);
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	for (auto i : xrange(2, 6)) {
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		setRom(i, 0);
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	}
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	setUnmapped(6);
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	setUnmapped(7);
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}
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const byte* RomHalnote::getReadCacheLine(uint16_t address) const
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{
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	if (subMapperEnabled && (0x7000 <= address) && (address < 0x8000)) {
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		// sub-mapper
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		int subBank = address < 0x7800 ? 0 : 1;
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		return &rom[0x80000 + subBanks[subBank] * 0x800 + (address & 0x7FF)];
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	} else {
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		// default mapper implementation
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		return Rom8kBBlocks::getReadCacheLine(address);
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	}
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}
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byte RomHalnote::readMem(uint16_t address, EmuTime /*time*/)
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{
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	// all reads are cacheable, reuse that implementation
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	return *RomHalnote::getReadCacheLine(address);
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}
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void RomHalnote::writeMem(uint16_t address, byte value, EmuTime /*time*/)
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{
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	if (address < 0x4000) {
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		// SRAM region
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		if (sramEnabled) {
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			sram->write(address, value);
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		}
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	} else if (address < 0xC000) {
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		if (address == one_of(0x77FF, 0x7FFF)) {
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			// sub-mapper bank switch region
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			int subBank = address < 0x7800 ? 0 : 1;
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			if (subBanks[subBank] != value) {
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				subBanks[subBank] = value;
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				if (subMapperEnabled) {
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					invalidateDeviceRCache(
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						0x7000 + subBank * 0x800, 0x800);
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				}
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			}
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		} else if ((address & 0x1FFF) == 0x0FFF) {
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			// normal bank switch region
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			auto bank = address >> 13; // 2-5
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			setRom(bank, value);
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			if (bank == 2) {
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				// sram enable/disable
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				bool newSramEnabled = (value & 0x80) != 0;
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				if (newSramEnabled != sramEnabled) {
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					sramEnabled = newSramEnabled;
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					if (sramEnabled) {
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						setBank(0, &(*sram)[0x0000], value);
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						setBank(1, &(*sram)[0x2000], value);
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					} else {
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						setUnmapped(0);
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						setUnmapped(1);
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					}
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					// 'R' is already handled
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					invalidateDeviceWCache(0x0000, 0x4000);
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				}
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			} else if (bank == 3) {
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				// sub-mapper enable/disable
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				subMapperEnabled = (value & 0x80) != 0;
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				if (subMapperEnabled) {
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					invalidateDeviceRCache(0x7000, 0x1000);
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				}
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			}
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		}
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	}
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}
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byte* RomHalnote::getWriteCacheLine(uint16_t address)
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{
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	if (address < 0x4000) {
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		// SRAM region
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		if (sramEnabled) {
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			return nullptr;
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		}
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	} else if (address < 0xC000) {
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		if ((address & CacheLine::HIGH) == one_of(0x77FF & CacheLine::HIGH,
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		                                          0x7FFF & CacheLine::HIGH)) {
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			// sub-mapper bank switch region
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			return nullptr;
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		} else if ((address & 0x1FFF & CacheLine::HIGH) ==
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		           (0x0FFF & CacheLine::HIGH)) {
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			// normal bank switch region
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			return nullptr;
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		}
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	}
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	return unmappedWrite.data();
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}
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template<typename Archive>
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void RomHalnote::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<Rom8kBBlocks>(*this);
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	ar.serialize("subBanks",         subBanks,
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	             "sramEnabled",      sramEnabled,
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	             "subMapperEnabled", subMapperEnabled);
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}
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INSTANTIATE_SERIALIZE_METHODS(RomHalnote);
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REGISTER_MSXDEVICE(RomHalnote, "RomHalnote");
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} // namespace openmsx