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◆ main openmsx / src / memory / CheckedRam.cc
3.1 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
e8555c89 Andy McCall 1 
#include "CheckedRam.hh"
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#include "DeviceConfig.hh"
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#include "GlobalSettings.hh"
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#include "MSXCPU.hh"
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#include "MSXMotherBoard.hh"
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#include "StringSetting.hh"
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#include "narrow.hh"
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#include "xrange.hh"
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#include <cassert>
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namespace openmsx {
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CheckedRam::CheckedRam(const DeviceConfig& config, const std::string& name,
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                       static_string_view description, size_t size)
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	: ram(config, name, description, size)
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	, msxcpu(config.getMotherBoard().getCPU())
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	, umrCallback(config.getGlobalSettings().getUMRCallBackSetting())
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{
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	umrCallback.getSetting().attach(*this);
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	init();
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}
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CheckedRam::~CheckedRam()
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{
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	umrCallback.getSetting().detach(*this);
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}
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uint8_t CheckedRam::read(size_t addr)
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{
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	if (size_t line = addr >> CacheLine::BITS;
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	    !completely_initialized_cacheline[line]) [[unlikely]] {
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		if (uninitialized[line][addr &  CacheLine::LOW]) [[unlikely]] {
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			umrCallback.execute(narrow<int>(addr), ram.getName());
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		}
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	}
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	return ram[addr];
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}
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const uint8_t* CheckedRam::getReadCacheLine(size_t addr) const
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{
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	return (completely_initialized_cacheline[addr >> CacheLine::BITS])
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	     ? &ram[addr] : nullptr;
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}
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uint8_t* CheckedRam::getWriteCacheLine(size_t addr)
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{
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	return (completely_initialized_cacheline[addr >> CacheLine::BITS])
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	     ? &ram[addr] : nullptr;
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}
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uint8_t* CheckedRam::getRWCacheLines(size_t addr, size_t size)
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{
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	// TODO optimize
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	size_t num = size >> CacheLine::BITS;
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	size_t first = addr >> CacheLine::BITS;
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	for (auto i : xrange(num)) {
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		if (!completely_initialized_cacheline[first + i]) {
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			return nullptr;
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		}
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	}
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	return &ram[addr];
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}
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void CheckedRam::write(size_t addr, const uint8_t value)
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{
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	if (size_t line = addr >> CacheLine::BITS;
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	    !completely_initialized_cacheline[line]) [[unlikely]] {
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		uninitialized[line][addr & CacheLine::LOW] = false;
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		if (uninitialized[line].none()) [[unlikely]] {
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			completely_initialized_cacheline[line] = true;
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			// This invalidates way too much stuff. But because
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			// (locally) we don't know exactly how this class ie
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			// being used in the MSXDevice, there's no easy way to
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			// figure out what exactly should be invalidated.
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			//
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			// This is anyway only a debug feature (usually it's
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			// not in use), therefor it's OK to implement this in a
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			// easy/slow way rather than complex/fast.
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			msxcpu.invalidateAllSlotsRWCache(0, 0x10000);
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		}
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	}
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	ram[addr] = value;
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}
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void CheckedRam::clear()
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{
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	ram.clear();
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	init();
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}
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void CheckedRam::init()
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{
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	auto lines = ram.size() / CacheLine::SIZE;
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	if (umrCallback.getValue().empty()) {
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		// there is no callback function,
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		// do as if everything is initialized
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		completely_initialized_cacheline.assign(lines, true);
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		// 'uninitialized' won't be accessed, so don't even allocate
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	} else {
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		// new callback function, forget about initialized areas
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		completely_initialized_cacheline.assign(lines, false);
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		std::bitset<CacheLine::SIZE> allTrue;
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		allTrue.set();
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		uninitialized.assign(lines, allTrue);
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	}
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	msxcpu.invalidateAllSlotsRWCache(0, 0x10000);
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}
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void CheckedRam::update(const Setting& setting) noexcept
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{
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	assert(&setting == &umrCallback.getSetting());
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	(void)setting;
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	init();
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}
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} // namespace openmsx