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◆ main openmsx / src / memory / RomNational.cc
3.5 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
e8555c89 Andy McCall 1 
#include "RomNational.hh"
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#include "SRAM.hh"
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#include "CacheLine.hh"
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#include "serialize.hh"
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#include "one_of.hh"
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#include "xrange.hh"
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#include <memory>
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namespace openmsx {
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RomNational::RomNational(const DeviceConfig& config, Rom&& rom_)
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	: Rom16kBBlocks(config, std::move(rom_))
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{
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	sram = std::make_unique<SRAM>(getName() + " SRAM", 0x1000, config);
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	reset(EmuTime::dummy());
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}
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void RomNational::reset(EmuTime /*time*/)
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{
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	control = 0;
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	for (auto region : xrange(4)) {
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		setRom(region, 0);
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		bankSelect[region] = 0;
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		invalidateDeviceRCache((region * 0x4000) + (0x3FF0 & CacheLine::HIGH),
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		                       CacheLine::SIZE);
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	}
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	sramAddr = 0; // TODO check this
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}
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byte RomNational::peekMem(uint16_t address, EmuTime time) const
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{
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	if ((control & 0x04) && ((address & 0x7FF9) == 0x7FF0)) {
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		// TODO check mirrored
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		// 7FF0 7FF2 7FF4 7FF6   bank select read back
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		int bank = (address & 6) / 2;
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		return bankSelect[bank];
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	}
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	if ((control & 0x02) && ((address & 0x3FFF) == 0x3FFD)) {
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		// SRAM read
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		return (*sram)[sramAddr & 0x0FFF];
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	}
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	return Rom16kBBlocks::peekMem(address, time);
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}
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byte RomNational::readMem(uint16_t address, EmuTime time)
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{
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	byte result = RomNational::peekMem(address, time);
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	if ((control & 0x02) && ((address & 0x3FFF) == 0x3FFD)) {
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		++sramAddr;
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	}
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	return result;
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}
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const byte* RomNational::getReadCacheLine(uint16_t address) const
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{
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	if ((0x3FF0 & CacheLine::HIGH) == (address & 0x3FFF)) {
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		return nullptr;
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	} else {
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		return Rom16kBBlocks::getReadCacheLine(address);
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	}
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}
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void RomNational::writeMem(uint16_t address, byte value, EmuTime /*time*/)
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{
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	// TODO bank switch address mirrored?
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	if (address == 0x6000) {
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		bankSelect[1] = value;
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		setRom(1, value); // !!
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		invalidateDeviceRCache(0x7FF0 & CacheLine::HIGH, CacheLine::SIZE);
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	} else if (address == 0x6400) {
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		bankSelect[0] = value;
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		setRom(0, value); // !!
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		invalidateDeviceRCache(0x3FF0 & CacheLine::HIGH, CacheLine::SIZE);
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	} else if (address == 0x7000) {
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		bankSelect[2] = value;
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		setRom(2, value);
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		invalidateDeviceRCache(0xBFF0 & CacheLine::HIGH, CacheLine::SIZE);
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	} else if (address == 0x7400) {
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		bankSelect[3] = value;
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		setRom(3, value);
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		invalidateDeviceRCache(0xFFF0 & CacheLine::HIGH, CacheLine::SIZE);
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	} else if (address == 0x7FF9) {
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		// write control byte
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		control = value;
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	} else if (control & 0x02) {
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		address &= 0x3FFF;
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		if (address == 0x3FFA) {
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			// SRAM address bits 23-16
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			sramAddr = (sramAddr & 0x00FFFF) | value << 16;
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		} else if (address == 0x3FFB) {
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			// SRAM address bits 15-8
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			sramAddr = (sramAddr & 0xFF00FF) | value << 8;
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		} else if (address == 0x3FFC) {
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			// SRAM address bits 7-0
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			sramAddr = (sramAddr & 0xFFFF00) | value;
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		} else if (address == 0x3FFD) {
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			sram->write((sramAddr++ & 0x0FFF), value);
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		}
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	}
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}
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byte* RomNational::getWriteCacheLine(uint16_t address)
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{
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	if (address == one_of(0x6000 & CacheLine::HIGH,
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	                      0x6400 & CacheLine::HIGH,
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	                      0x7000 & CacheLine::HIGH,
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	                      0x7400 & CacheLine::HIGH,
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	                      0x7FF9 & CacheLine::HIGH)) {
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		return nullptr;
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	} else if ((address & 0x3FFF) == (0x3FFA & CacheLine::HIGH)) {
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		return nullptr;
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	} else {
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		return unmappedWrite.data();
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	}
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}
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template<typename Archive>
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void RomNational::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<Rom16kBBlocks>(*this);
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	ar.serialize("control",    control,
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	             "sramAddr",   sramAddr,
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	             "bankSelect", bankSelect);
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}
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INSTANTIATE_SERIALIZE_METHODS(RomNational);
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REGISTER_MSXDEVICE(RomNational, "RomNational");
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} // namespace openmsx