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◆ main openmsx / src / memory / RomPanasonic.cc
5.5 KiB · C++ · last changed chore(): initial commit 1 month ago source blame history raw
e8555c89 Andy McCall 1 
#include "RomPanasonic.hh"
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#include "PanasonicMemory.hh"
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#include "SRAM.hh"
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#include "CacheLine.hh"
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#include "DeviceConfig.hh"
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#include "MSXMotherBoard.hh"
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#include "one_of.hh"
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#include "serialize.hh"
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#include "xrange.hh"
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#include <algorithm>
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#include <memory>
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namespace openmsx {
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const unsigned SRAM_BASE = 0x80;
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const unsigned RAM_BASE  = 0x180;
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RomPanasonic::RomPanasonic(const DeviceConfig& config, Rom&& rom_)
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	: Rom8kBBlocks(config, std::move(rom_))
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	, panasonicMem(getMotherBoard().getPanasonicMemory())
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{
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	unsigned sramSize = config.getChildDataAsInt("sramsize", 0);
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	if (sramSize) {
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		sram = std::make_unique<SRAM>(
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			getName() + " SRAM", sramSize * 1024, config);
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	}
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	if (config.getChildDataAsBool("sram-mirrored", false)) {
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		maxSRAMBank = SRAM_BASE + 8;
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	} else {
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		maxSRAMBank = SRAM_BASE + (sramSize / 8);
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	}
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	// Inform base class about PanasonicMemory (needed for serialization).
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	// This relies on the order of MSXDevice instantiation, the PanasonicRam
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	// device must be create before this one. (In the hardwareconfig.xml
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	// we added a device-reference from this device to the PanasonicRam
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	// device, this should protected against wrong future edits in the
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	// config file).
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	setExtraMemory({panasonicMem.getRamBlock(0), panasonicMem.getRamSize()});
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	reset(EmuTime::dummy());
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}
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void RomPanasonic::reset(EmuTime /*time*/)
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{
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	control = 0;
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	std::ranges::fill(bankSelect, 0);
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	for (auto region : xrange(8)) {
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		setRom(region, 0);
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	}
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	invalidateDeviceRCache(0x7FF0 & CacheLine::HIGH, CacheLine::SIZE);
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}
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byte RomPanasonic::peekMem(uint16_t address, EmuTime time) const
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{
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	if ((control & 0x04) && (0x7FF0 <= address) && (address < 0x7FF8)) {
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		// read mapper state (lower 8 bit)
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		return bankSelect[address & 7] & 0xFF;
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	} else if ((control & 0x10) && (address == 0x7FF8)) {
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		// read mapper state (9th bit)
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		byte result = 0;
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		for (int i = 7; i >= 0; i--) {
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			result <<= 1;
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			if (bankSelect[i] & 0x100) {
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				result++;
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			}
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		}
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		return result;
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	} else if ((control & 0x08) && (address == 0x7FF9)) {
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		// read control byte
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		return control;
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	} else {
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		return Rom8kBBlocks::peekMem(address, time);
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	}
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}
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byte RomPanasonic::readMem(uint16_t address, EmuTime time)
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{
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	return RomPanasonic::peekMem(address, time);
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}
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const byte* RomPanasonic::getReadCacheLine(uint16_t address) const
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{
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	if ((0x7FF0 & CacheLine::HIGH) == address) {
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		// TODO check mirrored
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		return nullptr;
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	} else {
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		return Rom8kBBlocks::getReadCacheLine(address);
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	}
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}
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void RomPanasonic::writeMem(uint16_t address, byte value, EmuTime /*time*/)
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{
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	if ((0x6000 <= address) && (address < 0x7FF0)) {
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		// set mapper state (lower 8 bits)
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		auto region = (address & 0x1C00) >> 10;
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		if (region == one_of(5, 6)) region ^= 3;
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		auto selectedBank = bankSelect[region];
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		auto newBank = (selectedBank & ~0xFF) | value;
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		changeBank(region, newBank);
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	} else if (address == 0x7FF8) {
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		// set mapper state (9th bit)
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		for (auto region : xrange(8)) {
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			if (value & 1) {
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				changeBank(region, bankSelect[region] |  0x100);
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			} else {
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				changeBank(region, bankSelect[region] & ~0x100);
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			}
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			value >>= 1;
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		}
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	} else if (address == 0x7FF9) {
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		// write control byte
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		control = value;
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	} else {
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		// Tested on real FS-A1GT:
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		//  SRAM/RAM can be written to from all regions, including e.g.
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		//  address 0x7ff0. (I didn't actually test 0xc000-0xffff).
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		auto region = address >> 13;
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		auto selectedBank = bankSelect[region];
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		if (sram && (SRAM_BASE <= selectedBank) &&
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		    (selectedBank < maxSRAMBank)) {
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			// SRAM
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			auto block = selectedBank - SRAM_BASE;
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			sram->write((block * 0x2000) | (address & 0x1FFF), value);
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		} else if (RAM_BASE <= selectedBank) {
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			// RAM
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			const_cast<byte*>(bankPtr[region])[address & 0x1FFF] = value;
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		}
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	}
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}
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byte* RomPanasonic::getWriteCacheLine(uint16_t address)
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{
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	if ((0x6000 <= address) && (address < 0x8000)) {
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		// mapper select (low/high), control
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		return nullptr;
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	} else {
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		auto region = address >> 13;
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		auto selectedBank = bankSelect[region];
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		if (sram && (SRAM_BASE <= selectedBank) &&
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		    (selectedBank < maxSRAMBank)) {
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			// SRAM
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			return nullptr;
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		} else if (RAM_BASE <= selectedBank) {
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			// RAM
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			return const_cast<byte*>(&bankPtr[region][address & 0x1FFF]);
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		} else {
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			return unmappedWrite.data();
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		}
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	}
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}
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void RomPanasonic::changeBank(unsigned region, unsigned bank)
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{
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	if (bank == bankSelect[region]) {
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		return;
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	}
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	bankSelect[region] = bank;
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	if (sram && (SRAM_BASE <= bank) && (bank < maxSRAMBank)) {
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		// SRAM
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		auto offset = (bank - SRAM_BASE) * size_t(0x2000);
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		if (auto sramSize = sram->size(); offset >= sramSize) {
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			offset &= (sramSize - 1);
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		}
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		// TODO RomBlock debuggable is only 8 bits, here bank is 9 bits
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		setBank(region, &sram->operator[](offset), narrow_cast<byte>(bank));
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	} else if (panasonicMem.getRamSize() && (RAM_BASE <= bank)) {
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		// RAM
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		// TODO RomBlock debuggable is only 8 bits, here bank is 9 bits
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		setBank(region, panasonicMem.getRamBlock(bank - RAM_BASE), narrow_cast<byte>(bank));
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	} else {
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		// ROM
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		setRom(region, bank);
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	}
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	invalidateDeviceWCache(0x2000 * region, 0x2000); // 'R' is already handled
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	if (region == 3) {
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		// don't pre-fill [0x7ff0, 0x7fff]
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		invalidateDeviceRCache(0x7FF0 & CacheLine::HIGH, CacheLine::SIZE);
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	}
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}
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template<typename Archive>
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void RomPanasonic::serialize(Archive& ar, unsigned /*version*/)
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{
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	ar.template serializeBase<Rom8kBBlocks>(*this);
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	ar.serialize("bankSelect", bankSelect,
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	             "control",    control);
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}
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INSTANTIATE_SERIALIZE_METHODS(RomPanasonic);
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REGISTER_MSXDEVICE(RomPanasonic, "RomPanasonic");
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} // namespace openmsx